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[PATCH v12 02/23] target/arm: Add PSTATE.ALLINT
From: |
Jinjie Ruan |
Subject: |
[PATCH v12 02/23] target/arm: Add PSTATE.ALLINT |
Date: |
Wed, 3 Apr 2024 10:15:50 +0000 |
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
ELx, with or without superpriority is masked.
As Richard suggested, place ALLINT bit in PSTATE in env->pstate.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
v5:
- Remove the ALLINT comment, as it is covered by "all other bits".
- Add Reviewed-by.
v4:
- Keep PSTATE.ALLINT in env->pstate but not env->allint.
- Update the commit message.
v3:
- Remove ALLINT dump in aarch64_cpu_dump_state().
- Update the commit message.
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index bc0c84873f..de740d223f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1430,6 +1430,7 @@ void pmu_init(ARMCPU *cpu);
#define PSTATE_D (1U << 9)
#define PSTATE_BTYPE (3U << 10)
#define PSTATE_SSBS (1U << 12)
+#define PSTATE_ALLINT (1U << 13)
#define PSTATE_IL (1U << 20)
#define PSTATE_SS (1U << 21)
#define PSTATE_PAN (1U << 22)
--
2.34.1
- Re: [PATCH v12 03/23] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, (continued)
- [PATCH v12 06/23] target/arm: Add support for Non-maskable Interrupt, Jinjie Ruan, 2024/04/03
- [PATCH v12 01/23] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI, Jinjie Ruan, 2024/04/03
- [PATCH v12 14/23] hw/intc/arm_gicv3: Add irq non-maskable property, Jinjie Ruan, 2024/04/03
- [PATCH v12 15/23] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Jinjie Ruan, 2024/04/03
- [PATCH v12 11/23] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/04/03
- [PATCH v12 04/23] target/arm: Implement ALLINT MSR (immediate), Jinjie Ruan, 2024/04/03
- [PATCH v12 02/23] target/arm: Add PSTATE.ALLINT,
Jinjie Ruan <=
- [PATCH v12 18/23] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read(), Jinjie Ruan, 2024/04/03
- [PATCH v12 13/23] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device, Jinjie Ruan, 2024/04/03
- [PATCH v12 21/23] hw/intc/arm_gicv3: Report the VINMI interrupt, Jinjie Ruan, 2024/04/03
- [PATCH v12 19/23] hw/intc/arm_gicv3: Implement NMI interrupt priority, Jinjie Ruan, 2024/04/03
- [PATCH v12 17/23] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Jinjie Ruan, 2024/04/03
- [PATCH v12 12/23] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/04/03