Re: [Qemu-ppc] Regression in ppc-softmmu when running HelenOS

[Alexander Graf]

On 14.03.2012, at 03:21, Mark Cave-Ayland wrote:

> On 13/03/12 12:03, Alexander Graf wrote:
> 
>> msr becomes srr1 (and masks the not-to-be-set bits out)
>> new_msr becomes the new MSR and only carries over MSR_ME from the current MSR
>> 
>> This looks correct to me. For reference, please check up page 811 on the 
>> PowerISA 2.06B:
>> 
>>   https://www.power.org/resources/downloads/PowerISA_V2.06B_V2_PUBLIC.pdf
> 
> Now this is very interesting as having read the above document, I had a very 
> different interpretation as to what should happen. From p.811:
> 
> 
> 1. SRR0 or HSRR0 is loaded with an instruction
> address that depends on the type of interrupt; see
> the specific interrupt description for details.
> 
> - This is already handled in the interrupt routine.
> 
> 2. Bits 33:36 and 42:47 of SRR1 or HSRR1 are
> loaded with information specific to the interrupt
> type.
> 
> - These bits are not relevant on PPC32 since MSR is only 32-bit.

PowerPC begins counting with the most significant bit, so they are in the 
32-bit range.


Alex