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Re: [Qemu-ppc] [PATCH 1/2] PPC: Fix interrupt MSR value within the PPC i
Re: [Qemu-ppc] [PATCH 1/2] PPC: Fix interrupt MSR value within the PPC interrupt handler.
Fri, 23 Mar 2012 13:50:51 +0000
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On 23/03/12 02:17, David Gibson wrote:
- /* new interrupt handler msr */
- new_msr = env->msr& ((target_ulong)1<< MSR_ME);
+ /* new interrupt handler msr (as per PowerISA 2.06B p.811 and p.814):
+ 1) force the following bits to zero
+ IR, DR, FE0, FE1, EE, BE, FP, PMM, PR, SE
+ 2) default the following bits to zero (can be overidden later on)
+ RI, HVB (note HVB is a different bit between PPC32/64) */
+ new_msr = env->msr& ~0xed36ULL& ~((target_ulong) MSR_HVB);
Both here and above, using the #defines rather than a hex constant
would be rather nicer. As Scott points out this probably need to be a
different mask for BookE, too.
Yes, that's fine. I'm happy to rework the patch, although as you see in
my response to Scott there is still some discussion required related to
whether bit inclusion or bit exclusion is used for the new MSR value. As
stated, I believe that bit exclusion is the approach suggested by the
Also, setting HVB to 0 doesn't make sense. Taking an interrupt can
turn hypervisor state *on* for certain interrupts, but it will never
turn it off.
Right. I think I determined this from trying to work out what should
happen to HVB by looking at the existing code, e.g.
/* new interrupt handler msr */
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
This will definitely clear HVB when processing the interrupt handler.
Again, as long as we can all agree on what the final approach should be,
I'm happy to implement it.