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Re: [Qemu-ppc] [PATCH 2/2] PPC: Fix TLB invalidation bug within the PPC
Re: [Qemu-ppc] [PATCH 2/2] PPC: Fix TLB invalidation bug within the PPC interrupt handler.
Wed, 28 Mar 2012 11:45:05 +1100
On Tue, Mar 27, 2012 at 04:41:55PM +0100, Mark Cave-Ayland wrote:
> Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB
> flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR
> bits at the start of the interrupt handler, the logic towards the end of the
> handler to force a TLB flush if either one of these bits were set would never
> be triggered.
> This patch simply changes the IR/DR bit check in the TLB flush logic to use
> the original MSR value (albeit with some interrupt-specific bits cleared) so
> that the IR/DR bits are preserved at the point where the check takes place.
> Signed-off-by: Mark Cave-Ayland <address@hidden>
Acked-by: David Gibson <address@hidden>
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!