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Re: [Qemu-ppc] [PATCH 08/15] openpic/fsl: critical interrupts ignore mas
From: |
Alexander Graf |
Subject: |
Re: [Qemu-ppc] [PATCH 08/15] openpic/fsl: critical interrupts ignore mask before v4.1 |
Date: |
Thu, 3 Jan 2013 19:37:37 +0100 |
On 22.12.2012, at 03:15, Scott Wood wrote:
> Signed-off-by: Scott Wood <address@hidden>
> ---
> hw/openpic.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/hw/openpic.c b/hw/openpic.c
> index 9d22e9c..268f312 100644
> --- a/hw/openpic.c
> +++ b/hw/openpic.c
> @@ -194,6 +194,7 @@ typedef struct IRQ_src_t {
> bool level; /* level-triggered */
> bool fslint; /* FSL internal interrupt -- level only */
> bool fslspecial; /* FSL timer/IPI interrupt, edge, no polarity */
> + bool nomask; /* critical interrupts ignore mask on some FSL MPICs */
This should be :1 - we have quite a big number of sources :).
Fixed up locally and applied to ppc-next.
Alex
> } IRQ_src_t;
>
> #define IVPR_MASK_SHIFT 31
> @@ -390,7 +391,7 @@ static void openpic_update_irq(OpenPICState *opp, int
> n_IRQ)
> DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
> return;
> }
> - if (src->ivpr & IVPR_MASK_MASK) {
> + if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
> /* Interrupt source is disabled */
> DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
> return;
> @@ -536,6 +537,7 @@ static inline void write_IRQreg_idr(OpenPICState *opp,
> int n_IRQ, uint32_t val)
> }
>
> src->output = OPENPIC_OUTPUT_CINT;
> + src->nomask = true;
> src->destmask = 0;
>
> for (i = 0; i < opp->nb_cpus; i++) {
> @@ -547,6 +549,7 @@ static inline void write_IRQreg_idr(OpenPICState *opp,
> int n_IRQ, uint32_t val)
> }
> } else {
> src->output = OPENPIC_OUTPUT_INT;
> + src->nomask = false;
> src->destmask = src->idr & normal_mask;
> }
> } else {
> --
> 1.7.9.5
>
>
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