Re: [Qemu-ppc] [Qemu-devel] KVM call minutes 2013-01-29 - Port I/O

[Alexander Graf]

On 30.01.2013, at 12:48, Peter Maydell wrote:

> On 30 January 2013 11:39, Andreas Färber <address@hidden> wrote:
>> Proposal by hpoussin was to move _list_add() code to ISADevice:
>> http://lists.gnu.org/archive/html/qemu-devel/2013-01/msg00508.html
>> 
>> Concerns:
>> * PCI devices (VGA, QXL) register I/O ports as well
>>  => above patches add dependency on ISABus to machines
>>     -> "<benh> no mac ever had one"
>>  => PCIDevice shouldn't use ISA API with NULL ISADevice
>> * Lack of avi: Who decides about memory API these days?
>> 
>> armbru and agraf concluded that moving this into ISA is wrong.
>> 
>> => I will drop the remaining ioport patches from above series.
>> 
>> Suggestions on how to proceed with tackling the issue are welcome.
> 
> How does this stuff work on real hardware? I would have
> expected that a PCI device registering the fact it has
> IO ports would have to do so via the PCI controller it
> is plugged into...

That's pretty much how it works for PCI hardware, yes.

For ISA like hardware, I asked Ben last night:

29-01-2013 23:41:10 > agraf: benh: hey ben :)
29-01-2013 23:41:50 > agraf: benh: do you remember if g3 beige (grackle) and/or 
U2 based macs had an actual ISA bus exposed through MMIO or whether it was PCI 
only with a PIO compat region mapped by the PCI controller?
29-01-2013 23:59:28 < address@hidden: agraf: no ISA
29-01-2013 23:59:48 < address@hidden: agraf: no mac ever had one
29-01-2013 23:59:57 > agraf: benh: well, MCP750 has one
30-01-2013 00:00:06 > agraf: benh: that's why I'm asking :)
30-01-2013 00:00:17 < address@hidden: mcp750 ? what is this ?
30-01-2013 00:00:28 > agraf: benh: some motorola soc
30-01-2013 00:00:39 < address@hidden: ah ok
30-01-2013 00:00:50 < address@hidden: mostly ISA is just hooked onto PCI anyway
30-01-2013 00:00:59 < address@hidden: ie, PCI cycles with low addresses land on 
ISA
30-01-2013 00:01:59 > agraf: benh: sounds tricky to model :)
30-01-2013 00:02:44 < address@hidden: that's also how it works on x86
30-01-2013 00:03:05 < address@hidden: dunno how it works on that specific SoC 
tho but that's how it's usually done
30-01-2013 00:04:36 > agraf: interesting - didn't know that :)
30-01-2013 00:04:51 > agraf: on x86 it's hard to see from a software pov, 
because everything's linear ;)
30-01-2013 00:26:27 < address@hidden: yeah, that's why x86 has a memory hole to 
make room for ISA
30-01-2013 00:26:40 < address@hidden: while usually on ppc we remap things with 
an offset so we don't have to punch a hole in ram

> My naive don't-know-much-about-portio suggestion is that this
> should work the same way as memory regions: each device
> provides portio regions, and the controller for the bus
> (ISA or PCI) exposes those to the next layer up, and
> something at board level maps it all into the right places.

Right. With the addition that on some boards, the PCI host controller which 
provides a portio map would also expose an ISABus for devices to plug in. At 
least if I understand Ben correctly.


Alex