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Re: [Qemu-ppc] [Qemu-devel] [PATCH 01/10] target-ppc: optimize fabs, fna
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-ppc] [Qemu-devel] [PATCH 01/10] target-ppc: optimize fabs, fnabs, fneg |
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Date: |
Sat, 13 Apr 2013 14:20:10 +0100 |
On 13 April 2013 13:47, Aurelien Jarno <address@hidden> wrote:
> fabs, fnabs and fneg are just flipping the bit sign of an FP register,
> this can be implemented in TCG instead of using softfloat.
> + tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
> + ~(1LL << 63));
"1LL << 63" is undefined behaviour; you probably want "1ULL << 63".
-- PMM
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 04/10] target-ppc: emulate cmpb instruction, (continued)
- [Qemu-ppc] [PATCH 06/10] target-ppc: emulate fcpsgn instruction, Aurelien Jarno, 2013/04/13
- [Qemu-ppc] [PATCH 05/10] target-ppc: emulate prtyw and prtyd instructions, Aurelien Jarno, 2013/04/13
- [Qemu-ppc] [PATCH 03/10] target-ppc: add instruction flags for Book I 2.05, Aurelien Jarno, 2013/04/13
- [Qemu-ppc] [PATCH 02/10] disas: Disassemble all ppc insns for the guest, Aurelien Jarno, 2013/04/13
- [Qemu-ppc] [PATCH 01/10] target-ppc: optimize fabs, fnabs, fneg, Aurelien Jarno, 2013/04/13
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 01/10] target-ppc: optimize fabs, fnabs, fneg,
Peter Maydell <=
- [Qemu-ppc] [PATCH 10/10] target-ppc: add support for extended mtfsf/mtfsfi forms, Aurelien Jarno, 2013/04/13
- Re: [Qemu-ppc] [PATCH 00/10] target-ppc: emulate Power ISA 2.05 instructions, Alexander Graf, 2013/04/19