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[Qemu-ppc] [PATCH 21/30] target-ppc: optimize fabs, fnabs, fneg
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PATCH 21/30] target-ppc: optimize fabs, fnabs, fneg |
Date: |
Fri, 26 Apr 2013 20:21:40 +0200 |
From: Aurelien Jarno <address@hidden>
fabs, fnabs and fneg are just flipping the bit sign of an FP register,
this can be implemented in TCG instead of using softfloat.
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/fpu_helper.c | 31 -------------------------------
target-ppc/helper.h | 3 ---
target-ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++------
3 files changed, 34 insertions(+), 40 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 1e141fb..1f0eeab 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -596,37 +596,6 @@ uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1,
uint64_t arg2)
return farg1.ll;
}
-/* fabs */
-uint64_t helper_fabs(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
-
- farg.ll = arg;
- farg.d = float64_abs(farg.d);
- return farg.ll;
-}
-
-/* fnabs */
-uint64_t helper_fnabs(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
-
- farg.ll = arg;
- farg.d = float64_abs(farg.d);
- farg.d = float64_chs(farg.d);
- return farg.ll;
-}
-
-/* fneg */
-uint64_t helper_fneg(CPUPPCState *env, uint64_t arg)
-{
- CPU_DoubleU farg;
-
- farg.ll = arg;
- farg.d = float64_chs(farg.d);
- return farg.ll;
-}
-
/* fctiw - fctiw. */
uint64_t helper_fctiw(CPUPPCState *env, uint64_t arg)
{
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index d33ee66..07397b2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -80,9 +80,6 @@ DEF_HELPER_4(fmadd, i64, env, i64, i64, i64)
DEF_HELPER_4(fmsub, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64)
DEF_HELPER_4(fnmsub, i64, env, i64, i64, i64)
-DEF_HELPER_2(fabs, i64, env, i64)
-DEF_HELPER_2(fnabs, i64, env, i64)
-DEF_HELPER_2(fneg, i64, env, i64)
DEF_HELPER_2(fsqrt, i64, env, i64)
DEF_HELPER_2(fre, i64, env, i64)
DEF_HELPER_2(fres, i64, env, i64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 362ca3a..6cc7893 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2170,7 +2170,16 @@ static void gen_fcmpu(DisasContext *ctx)
/*** Floating-point move ***/
/* fabs */
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
-GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
+static void gen_fabs(DisasContext *ctx)
+{
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
+ ~(1ULL << 63));
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
/* fmr - fmr. */
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
@@ -2186,10 +2195,29 @@ static void gen_fmr(DisasContext *ctx)
/* fnabs */
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
-GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
+static void gen_fnabs(DisasContext *ctx)
+{
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
+ 1ULL << 63);
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
+
/* fneg */
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
-GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
+static void gen_fneg(DisasContext *ctx)
+{
+ if (unlikely(!ctx->fpu_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_FPU);
+ return;
+ }
+ tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
+ 1ULL << 63);
+ gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
+}
/*** Floating-Point status & ctrl register ***/
@@ -8485,7 +8513,10 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0,
PPC_FLOAT_FSQRT),
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
+GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
+GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
@@ -8842,9 +8873,6 @@ GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
-GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
-GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
-GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
#undef GEN_LD
#undef GEN_LDU
--
1.6.0.2
- [Qemu-ppc] [PATCH 11/30] PPC: Fix compile with profiling enabled, (continued)
- [Qemu-ppc] [PATCH 11/30] PPC: Fix compile with profiling enabled, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 05/30] PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 20/30] PPC: Fix dcbz for linux-user on 970, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 22/30] disas: Disassemble all ppc insns for the guest, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 23/30] target-ppc: add instruction flags for Book I 2.05, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 29/30] target-ppc: emulate store doubleword pair instructions, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 24/30] target-ppc: emulate cmpb instruction, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 28/30] target-ppc: emulate load doubleword pair instructions, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 26/30] target-ppc: emulate fcpsgn instruction, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 25/30] target-ppc: emulate prtyw and prtyd instructions, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 21/30] target-ppc: optimize fabs, fnabs, fneg,
Alexander Graf <=
- [Qemu-ppc] [PATCH 19/30] powerpc: correctly handle fpu exceptions., Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 27/30] target-ppc: emulate lfiwax instruction, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 15/30] pseries: Fix some small errors in XICS logic, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 14/30] target-ppc: Add more stubs for POWER7 PMU registers, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 18/30] pseries: Generate device paths for VIO devices, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 09/30] Enable kvm emulated watchdog, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 12/30] pseries: Fix incorrect calculation of RMA size in certain configurations, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 03/30] PPC: Remove env->hreset_excp_prefix, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 30/30] target-ppc: add support for extended mtfsf/mtfsfi forms, Alexander Graf, 2013/04/26
- [Qemu-ppc] [PATCH 13/30] pseries: Fixes and enhancements to L1 cache properties, Alexander Graf, 2013/04/26