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[Qemu-ppc] [V2 PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [V2 PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06 |
Date: |
Wed, 11 Dec 2013 13:16:21 -0600 |
This patch adds a flag for base instruction additions to Power ISA
2.06B. The flag will be used to identify/select basic Book I and
Book II instructions that were newly added in that revision of the
architecture. The flag will not be used for VSX or Altivec.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/cpu.h | 4 +++-
target-ppc/translate_init.c | 6 ++++--
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 0abc848..fe3aace 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1877,9 +1877,11 @@ enum {
PPC2_ISA205 = 0x0000000000000020ULL,
/* VSX additions in ISA 2.07 */
PPC2_VSX207 = 0x0000000000000040ULL,
+ /* Book I 2.06B PowerPC specification (base instructions) */
+ PPC2_ISA206 = 0x0000000000000080ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
- PPC2_ISA205 | PPC2_VSX207)
+ PPC2_ISA205 | PPC2_VSX207 | PPC2_ISA206)
};
/*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e14ab63..491e56c 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7234,7 +7234,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
- pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
+ PPC2_ISA206;
pcc->msr_mask = 0x800000000284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7270,7 +7271,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
- pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
+ PPC2_ISA206;
pcc->msr_mask = 0x800000000284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
--
1.7.1
- [Qemu-ppc] [V2 PATCH 00/18] target-ppc: Base ISA V2.06 for Power7/Power8, Tom Musta, 2013/12/11
- [Qemu-ppc] [V2 PATCH 01/18] target-ppc: Add Flag for Power ISA V2.06,
Tom Musta <=
- [Qemu-ppc] [V2 PATCH 02/18] target-ppc: Add ISA2.06 bpermd Instruction, Tom Musta, 2013/12/11
- [Qemu-ppc] [V2 PATCH 03/18] target-ppc: Add ISA2.06 divdeu[o] Instructions, Tom Musta, 2013/12/11
- [Qemu-ppc] [V2 PATCH 04/18] target-ppc: Add ISA2.06 divde[o] Instructions, Tom Musta, 2013/12/11
- [Qemu-ppc] [V2 PATCH 05/18] target-ppc: Add ISA 2.06 divwe[u][o] Instructions, Tom Musta, 2013/12/11
- [Qemu-ppc] [V2 PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions, Tom Musta, 2013/12/11
- [Qemu-ppc] [V2 PATCH 06/18] target-ppc: Add ISA2.06 lbarx, lharx Instructions, Tom Musta, 2013/12/11
- [Qemu-ppc] [V2 PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions, Tom Musta, 2013/12/11
- [Qemu-ppc] [V2 PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64, Tom Musta, 2013/12/11
- [Qemu-ppc] [V2 PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero, Tom Musta, 2013/12/11