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[Qemu-ppc] [V4 PATCH 17/22] target-ppc: Fix and enable fri[mnpz]
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [V4 PATCH 17/22] target-ppc: Fix and enable fri[mnpz] |
Date: |
Tue, 7 Jan 2014 10:06:05 -0600 |
The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines.
Also, the existing helper is modified to correctly handle some of
the boundary cases (NaNs and the inexact flag).
Signed-off-by: Tom Musta <address@hidden>
---
V4: frin changed to use "ties away" rounding mode per Richard Henderson's
review. Modified NaN handling. Proper handling of stickiness of
the inexact flag. Added to P7+ model.
target-ppc/fpu_helper.c | 18 +++++++++++-------
target-ppc/translate_init.c | 3 +++
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 4985f53..bb84852 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -669,24 +669,28 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_t
arg,
if (unlikely(float64_is_signaling_nan(farg.d))) {
/* sNaN round */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
- POWERPC_EXCP_FP_VXCVI, 1);
- } else if (unlikely(float64_is_quiet_nan(farg.d) ||
- float64_is_infinity(farg.d))) {
- /* qNan / infinity round */
- farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);
+ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ farg.ll = arg | 0x0008000000000000ul;
} else {
+ int inexact = get_float_exception_flags(&env->fp_status) &
+ float_flag_inexact;
set_float_rounding_mode(rounding_mode, &env->fp_status);
farg.ll = float64_round_to_int(farg.d, &env->fp_status);
/* Restore rounding mode from FPSCR */
fpscr_set_rounding_mode(env);
+
+ /* fri* does not set FPSCR[XX] */
+ if (!inexact) {
+ env->fp_status.float_exception_flags &= ~float_flag_inexact;
+ }
}
+ helper_float_check_status(env);
return farg.ll;
}
uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
{
- return do_fri(env, arg, float_round_nearest_even);
+ return do_fri(env, arg, float_round_ties_away);
}
uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 3fb849b..ad53fa7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7230,6 +7230,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
@@ -7270,6 +7271,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
@@ -7310,6 +7312,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
PPC_FLOAT_STFIWX |
+ PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
--
1.7.1
- [Qemu-ppc] [V4 PATCH 08/22] target-ppc: Add ISA2.06 lbarx, lharx Instructions, (continued)
- [Qemu-ppc] [V4 PATCH 08/22] target-ppc: Add ISA2.06 lbarx, lharx Instructions, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 14/22] softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 10/22] target-ppc: Add Flag for ISA V2.06 Floating Point Conversion, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 15/22] softfloat: Refactor code handling various rounding modes, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 11/22] target-ppc: Add ISA2.06 Float to Integer Instructions, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 09/22] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 12/22] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 16/22] softfloat: Add support for ties-away rounding, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 17/22] target-ppc: Fix and enable fri[mnpz],
Tom Musta <=
- [Qemu-ppc] [V4 PATCH 18/22] target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 19/22] target-ppc: Add ISA 2.06 ftdiv Instruction, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 20/22] target-ppc: Add ISA 2.06 ftsqrt, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 22/22] target-ppc: Add ISA2.06 lfiwzx Instruction, Tom Musta, 2014/01/07
- [Qemu-ppc] [V4 PATCH 21/22] target-ppc: Enable frsqrtes on Power7 and Power8, Tom Musta, 2014/01/07
- Re: [Qemu-ppc] [V4 PATCH 00/22] target-ppc: Base ISA V2.06 for Power7/Power8, Alexander Graf, 2014/01/27