Re: [Qemu-ppc] [PATCH 7/8] target-ppc: Add Load Quadword and Reserve

[Alexander Graf]

On 27.01.2014, at 18:54, Tom Musta <address@hidden> wrote:

> This patch adds the Load Quadword and Reserve (lqarx) instruction,
> which is new in Power ISA 2.07.
> 
> Signed-off-by: Tom Musta <address@hidden>
> ---
> target-ppc/translate.c |   34 ++++++++++++++++++++++++++++++++++
> 1 files changed, 34 insertions(+), 0 deletions(-)
> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index bb1dc82..589cee9 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -3361,6 +3361,39 @@ STCX(stwcx_, 4);
> /* ldarx */
> LARX(ldarx, 8, ld64);
> 
> +/* lqarx */
> +static void gen_lqarx(DisasContext *ctx)
> +{
> +    TCGv EA;
> +    int rd = rD(ctx->opcode);
> +    TCGv gpr1, gpr2;
> +
> +    if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
> +                 (rd == rB(ctx->opcode)))) {
> +        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> +        return;
> +    }
> +
> +    gen_set_access_type(ctx, ACCESS_RES);
> +    EA = tcg_temp_local_new();
> +    gen_addr_reg_index(ctx, EA);
> +    gen_check_align(ctx, EA, 15);
> +    if (unlikely(ctx->le_mode)) {
> +        gpr1 = cpu_gpr[rd+1];
> +        gpr2 = cpu_gpr[rd];
> +    } else {
> +        gpr1 = cpu_gpr[rd];
> +        gpr2 = cpu_gpr[rd+1];
> +    }
> +    gen_qemu_ld64(ctx, gpr1, EA);
> +    tcg_gen_mov_tl(cpu_reserve, EA);
> +    tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));

I suppose it's ok to only store the first 64bits as reserved?


Alex