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Re: [Qemu-ppc] PPC440x5 with an external APU FPU double precision


From: Tom Musta
Subject: Re: [Qemu-ppc] PPC440x5 with an external APU FPU double precision
Date: Mon, 08 Sep 2014 07:30:25 -0500
User-agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0

On 9/6/2014 2:03 AM, Pierre Mallard wrote:
> Hi,
> 
> I need to add floating point and double precision ability to PPC440x5 which 
> have an optional APU FPU.
> 
> I have therefore a few questions prior to posting any patch :
> 
> 1) Is adding PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | PPC_FLOAT_FSQRT | 
> PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX to insns_flags is OK or should I use 
> additional CPU parameters to prevent adding floating point capabilities to 
> all PPC440x5 ?
> 

The tricky bit here, of course, is that the 440 core does not inherently 
support FP.  As you said, the FP support comes via an APU.  So the risk of 
doing this is to other users of the 440 model that might expect FP instructions 
to be illegal.

> 2) I have encounter some double precision mnemonics that seemed to be 
> reserved to 64bits processor : fctidz for instance. Translate macro 
> definition of such mnemonics are reserved to TARGET_PPC64 and mnemonics type 
> required to have PPC_64B in insns flags. 
> Since PPC440x5 is a 32bits processor but the APU FPU is able to perform 
> double precision computation I would like to remove TARGET_PPC64 limitation 
> and change type to PPC_FLOAT_DOUBLE to enable 32 bits processor with double 
> precision floating point mnemonics. 
> By the way, adding the PPC_FLOAT_DOUBLE flag requires to remove one of the 
> PPC_FLOAT flag since there is no much bit available in insns flag, I have 
> done this by setting PPC_FLOAT_FRES and PPC_FLOAT_FSEL to same value since 
> they seem to be always used
> together.

The fctidz instruction is (I think) a TARGET_PPC64 instruction because it 
converts a double precision FPR to a 64-bit *integer*.  That said, the ISA only 
identifies fctidz as part of the FP category and does not seem to restrict it 
to 64 bit.  The
FreeScale e500 is a 32-bit core that supports FP in general but does not 
support the fctid* instructions.  Does your APU really support this 
instruction?  If yes, this may need to be done via instruction flags rather 
than the TARGET_PPC64 identifier.
> 
> 3) Shall I post the patch and continue the discussion on the patch's thread 
> or is it better to discuss before posting any patch ?
> 

Yes.

> Thanks for your help and advice.
> 
> Pierre
> 




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