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Re: [Qemu-ppc] [PATCH v3] tcg/ppc: Improve unaligned load/store handling


From: Aurelien Jarno
Subject: Re: [Qemu-ppc] [PATCH v3] tcg/ppc: Improve unaligned load/store handling on 64-bit backend
Date: Tue, 21 Jul 2015 17:29:12 +0200
User-agent: Mutt/1.5.23 (2014-03-12)

On 2015-07-21 15:19, Benjamin Herrenschmidt wrote:
> Currently, we get to the slow path for any unaligned access in the
> backend, because we effectively preserve the bottom address bits
> below the alignment requirement when comparing with the TLB entry,
> so any non-0 bit there will cause the compare to fail.
> 
> For the same number of instructions, we can instead add the access
> size - 1 to the address and stick to clearing all the bottom bits.
> 
> That means that normal unaligned accesses will not fallback (the HW
> will handle them fine). Only when crossing a page boundary well we
> end up having a mismatch because we'll end up pointing to the next
> page which cannot possibly be in that same TLB entry.
> 
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>

Reviewed-by: Aurelien Jarno <address@hidden>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
address@hidden                 http://www.aurel32.net



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