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[Qemu-ppc] [PATCH v2 4/5] target-ppc: add vector bit permute doubleword
From: |
Rajalakshmi Srinivasaraghavan |
Subject: |
[Qemu-ppc] [PATCH v2 4/5] target-ppc: add vector bit permute doubleword instruction |
Date: |
Tue, 9 Aug 2016 15:42:19 +0530 |
Add vbpermd instruction from ISA 3.0.
Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 20 ++++++++++++++++++++
target-ppc/translate/vmx-impl.c | 1 +
target-ppc/translate/vmx-ops.c | 1 +
4 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 6e6e7b3..d1d9418 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -335,6 +335,7 @@ DEF_HELPER_2(vpopcntb, void, avr, avr)
DEF_HELPER_2(vpopcnth, void, avr, avr)
DEF_HELPER_2(vpopcntw, void, avr, avr)
DEF_HELPER_2(vpopcntd, void, avr, avr)
+DEF_HELPER_3(vbpermd, void, avr, avr, avr)
DEF_HELPER_3(vbpermq, void, avr, avr, avr)
DEF_HELPER_2(vgbbd, void, avr, avr)
DEF_HELPER_3(vpmsumb, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 188ac6f..d6f26bb 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1134,6 +1134,26 @@ void helper_vperm(CPUPPCState *env, ppc_avr_t *r,
ppc_avr_t *a, ppc_avr_t *b,
#define VBPERMQ_DW(index) (((index) & 0x40) == 0)
#endif
+void helper_vbpermd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i, j;
+ uint64_t perm = 0;
+
+ VECTOR_FOR_INORDER_I(i, u64) {
+ perm = 0;
+ for (j = 0; j < 8; j++) {
+ int index = VBPERMQ_INDEX(b, (i * 8) + j);
+ if (index < 64) {
+ uint64_t mask = (1ull << (63 - (index & 0x3F)));
+ if (a->u64[VBPERMQ_DW(index)] & mask) {
+ perm |= (0x80 >> j);
+ }
+ }
+ }
+ r->u64[i] = perm;
+ }
+}
+
void helper_vbpermq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c
index 2cf8c8f..5ddff58 100644
--- a/target-ppc/translate/vmx-impl.c
+++ b/target-ppc/translate/vmx-impl.c
@@ -754,6 +754,7 @@ GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM(vbpermd, 6, 23);
GEN_VXFORM(vbpermq, 6, 21);
GEN_VXFORM_NOA(vgbbd, 6, 20);
GEN_VXFORM(vpmsumb, 4, 16)
diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c
index 5b2826e..32bd533 100644
--- a/target-ppc/translate/vmx-ops.c
+++ b/target-ppc/translate/vmx-ops.c
@@ -261,6 +261,7 @@ GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE,
PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_300(vbpermd, 6, 23),
GEN_VXFORM_207(vbpermq, 6, 21),
GEN_VXFORM_207(vgbbd, 6, 20),
GEN_VXFORM_207(vpmsumb, 4, 16),
--
1.7.1
- [Qemu-ppc] [PATCH 2/5] target-ppc: add vector extract instructions, (continued)
- [Qemu-ppc] [PATCH 2/5] target-ppc: add vector extract instructions, Rajalakshmi Srinivasaraghavan, 2016/08/01
- [Qemu-ppc] [PATCH 3/5] target-ppc: add vector count trailing zeros instructions, Rajalakshmi Srinivasaraghavan, 2016/08/01
- [Qemu-ppc] [PATCH 4/5] target-ppc: add vector bit permute doubleword instruction, Rajalakshmi Srinivasaraghavan, 2016/08/01
- [Qemu-ppc] [PATCH 5/5] target-ppc: add vector permute right indexed instruction, Rajalakshmi Srinivasaraghavan, 2016/08/01
- [Qemu-ppc] [PATCH 0/5] POWER9 TCG enablement - part3, Rajalakshmi Srinivasaraghavan, 2016/08/09
- [Qemu-ppc] [PATCH v2 2/5] target-ppc: add vector extract instructions, Rajalakshmi Srinivasaraghavan, 2016/08/09
- [Qemu-ppc] [PATCH v2 4/5] target-ppc: add vector bit permute doubleword instruction,
Rajalakshmi Srinivasaraghavan <=
- [Qemu-ppc] [PATCH v2 3/5] target-ppc: add vector count trailing zeros instructions, Rajalakshmi Srinivasaraghavan, 2016/08/09
- [Qemu-ppc] [PATCH v2 5/5] target-ppc: add vector permute right indexed instruction, Rajalakshmi Srinivasaraghavan, 2016/08/09