[Qemu-ppc] [PATCH v2 00/17] POWER9 TCG enablements - part4

[Nikunj A Dadhania]

1) Consolidate Load/Store operations using tcg_gen_qemu_ld/st functions
2) This series contains 10 new instructions for POWER9 ISA3.0
   Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x.

Patches:
 01-09:  Cleanup load/store operations in ppc translator 
    10:  xxspltib: VSX Vector Splat Immediate Byte
    11:  darn: Deliver a random number
    12:  lxsibzx - Load VSX Scalar as Integer Byte & Zero Indexed
         lxsihzx - Load VSX Scalar as Integer Halfword & Zero Indexed
    13:  stxsibx - Store VSX Scalar as Integer Byte Indexed
         stxsihx - Store VSX Scalar as Integer Halfword Indexed
    14:  lxvw4x - improve implementation
    15:  lxvb16x: Load VSX Vector Byte*16
         lxvh8x:  Load VSX Vector Halfword*8
    16:  stxv4x - improve implementation
    17:  stxvb16x: Store VSX Vector Byte*16
         stxvh8x:  Store VSX Vector Halfword*8

Series also available here: https://github.com/nikunjad/qemu/tree/p9-tcg

Changelog:
v1: 
* More load/store cleanups in byte reverse routines
* ld64/st64 converted to newer macro and updated call sites
* Cleanup load with reservation and store conditional
* Return invalid random for darn instruction

v0:
* darn - read /dev/random to get the random number
* xxspltib - make is PPC64 only
* Consolidate load/store operations and use macros to generate qemu_st/ld
* Simplify load/store vsx endian manipulation

Nikunj A Dadhania (16):
  target-ppc: consolidate load operations
  target-ppc: convert ld64 to use new macro
  target-ppc: convert ld[16,32,64]ur to use new macro
  target-ppc: consolidate store operations
  target-ppc: convert st64 to use new macro
  target-ppc: convert st[16,32,64]r to use new macro
  target-ppc: consolidate load with reservation
  target-ppc: move out stqcx impementation
  target-ppc: consolidate store conditional
  target-ppc: add xxspltib instruction
  target-ppc: add lxsi[bw]zx instruction
  target-ppc: add stxsi[bh]x instruction
  target-ppc: improve lxvw4x implementation
  target-ppc: add lxvb16x and lxvh8x
  target-ppc: improve stxvw4x implementation
  target-ppc: add stxvb16x and stxvh8x

Ravi Bangoria (1):
  target-ppc: implement darn instruction

 target-ppc/helper.h                 |   4 +
 target-ppc/int_helper.c             |  16 ++
 target-ppc/mem_helper.c             |  11 ++
 target-ppc/translate.c              | 379 +++++++++++++++++-------------------
 target-ppc/translate/fp-impl.inc.c  |  84 ++++----
 target-ppc/translate/fp-ops.inc.c   |   2 +-
 target-ppc/translate/spe-impl.inc.c |   4 +-
 target-ppc/translate/vmx-impl.inc.c |  24 +--
 target-ppc/translate/vsx-impl.inc.c | 208 ++++++++++++++++----
 target-ppc/translate/vsx-ops.inc.c  |  13 ++
 10 files changed, 460 insertions(+), 285 deletions(-)

-- 
2.7.4