[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PULL 26/66] ppc: FP exceptions are always precise
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 26/66] ppc: FP exceptions are always precise |
Date: |
Tue, 6 Sep 2016 13:42:36 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
We don't implement imprecise FP exceptions and using store_current
which sets SRR1 to the *previous* instruction never makes sense
for these. So let's be truthful and make them precise, which is
allowed by the architecture.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/excp_helper.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 96c6fd9..02d9e79 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -274,12 +274,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
env->error_code = 0;
return;
}
+
+ /* FP exceptions always have NIP pointing to the faulting
+ * instruction, so always use store_next and claim we are
+ * precise in the MSR.
+ */
msr |= 0x00100000;
- if (msr_fe0 == msr_fe1) {
- goto store_next;
- }
- msr |= 0x00010000;
- break;
+ goto store_next;
case POWERPC_EXCP_INVAL:
LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
msr |= 0x00080000;
--
2.7.4
- [Qemu-ppc] [PULL 63/66] ppc: Improve a few more helper flags, (continued)
- [Qemu-ppc] [PULL 63/66] ppc: Improve a few more helper flags, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 55/66] hw/ppc: use error_report instead of fprintf, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 58/66] ppc: Fix catching some segfaults in user mode, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 54/66] ppc: Rename #include'd .c files to .inc.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 07/66] target-ppc: add modulo word operations, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 32/66] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 51/66] target-ppc: add vslv instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 60/66] ppc: Don't generate dead code on unconditional branches, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 17/66] ppc: Move classic fp ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 05/66] target-ppc: adding addpcis instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 26/66] ppc: FP exceptions are always precise,
David Gibson <=
- [Qemu-ppc] [PULL 33/66] ppc: Don't update NIP in facility unavailable interrupts, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 13/66] target-ppc: add maddld instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 11/66] target-ppc: add cmpeqb instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 29/66] ppc: Make tlb_fill() use new exception helper, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 31/66] ppc: Fix source NIP on SLB related interrupts, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 25/66] ppc: Don't update the NIP in floating point generated code, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 19/66] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 22/66] ppc: Rename fload_invalid_op_excp to float_invalid_op_excp, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 40/66] ppc: Speed up dcbz, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 30/66] ppc: Rework NIP updates vs. exception generation, David Gibson, 2016/09/05