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[Qemu-ppc] [PULL 35/66] ppc: Don't update NIP on conditional trap instru
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 35/66] ppc: Don't update NIP on conditional trap instructions |
Date: |
Tue, 6 Sep 2016 13:42:45 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
This is no longer necessary as the helpers will properly retrieve
the return address when needed.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/excp_helper.c | 6 ++++--
target-ppc/translate.c | 8 --------
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index d31eece..882d529 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -1031,7 +1031,8 @@ void helper_tw(CPUPPCState *env, target_ulong arg1,
target_ulong arg2,
((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
- raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_TRAP, GETPC());
}
}
@@ -1044,7 +1045,8 @@ void helper_td(CPUPPCState *env, target_ulong arg1,
target_ulong arg2,
((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
- raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_TRAP, GETPC());
}
}
#endif
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f75cdc6..93cd98c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3580,8 +3580,6 @@ static void gen_sc(DisasContext *ctx)
static void gen_tw(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
- /* Update the nip since this might generate a trap exception */
- gen_update_nip(ctx, ctx->nip - 4);
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
tcg_temp_free_i32(t0);
@@ -3592,8 +3590,6 @@ static void gen_twi(DisasContext *ctx)
{
TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
- /* Update the nip since this might generate a trap exception */
- gen_update_nip(ctx, ctx->nip - 4);
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
tcg_temp_free(t0);
tcg_temp_free_i32(t1);
@@ -3604,8 +3600,6 @@ static void gen_twi(DisasContext *ctx)
static void gen_td(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
- /* Update the nip since this might generate a trap exception */
- gen_update_nip(ctx, ctx->nip - 4);
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
tcg_temp_free_i32(t0);
@@ -3616,8 +3610,6 @@ static void gen_tdi(DisasContext *ctx)
{
TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
- /* Update the nip since this might generate a trap exception */
- gen_update_nip(ctx, ctx->nip - 4);
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
tcg_temp_free(t0);
tcg_temp_free_i32(t1);
--
2.7.4
- [Qemu-ppc] [PULL 19/66] ppc: Move DFP ops out of translate.c, (continued)
- [Qemu-ppc] [PULL 19/66] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 22/66] ppc: Rename fload_invalid_op_excp to float_invalid_op_excp, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 40/66] ppc: Speed up dcbz, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 30/66] ppc: Rework NIP updates vs. exception generation, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 47/66] target-ppc: implement branch-less divd[o][.], David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 56/66] hw/ppc: add a ppc_create_page_sizes_prop() helper routine, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 45/66] ppc: Speed up load/store multiple, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 50/66] target-ppc: add vcmpnez[b, h, w][.] instructions, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 65/66] tests: Resort check-qtest entries in Makefile.include, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 64/66] spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 35/66] ppc: Don't update NIP on conditional trap instructions,
David Gibson <=
- [Qemu-ppc] [PULL 52/66] target-ppc: add vsrv instruction, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 41/66] ppc: Fix CFAR updates, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 66/66] tests: Check serial output of firmware boot of some machines, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 20/66] ppc: Move VMX ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 21/66] ppc: Move VSX ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-ppc] [PULL 18/66] ppc: Move embedded spe ops out of translate.c, David Gibson, 2016/09/05
- Re: [Qemu-ppc] [Qemu-devel] [PULL 00/66] ppc-for-2.8 queue 20160906, no-reply, 2016/09/06