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Re: [Qemu-ppc] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions
From: |
Richard Henderson |
Subject: |
Re: [Qemu-ppc] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions |
Date: |
Wed, 28 Sep 2016 09:54:34 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 |
On 09/27/2016 10:45 PM, Rajalakshmi Srinivasaraghavan wrote:
> +#if defined(HOST_WORDS_BIGENDIAN)
> +#define VEXTULX_DO(name, elem) \
> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
> +{ \
> + target_ulong r = 0; \
> + int i; \
> + int index = a & 0xf; \
> + for (i = 0; i < elem; i++) { \
> + r = r << 8; \
> + if (index + i <= 15) { \
> + r = r | b->u8[index + i]; \
> + } \
> + } \
> + return r; \
> +}
> +#else
> +#define VEXTULX_DO(name, elem) \
> +target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
> +{ \
> + target_ulong r = 0; \
> + int i; \
> + int index = 15 - (a & 0xf); \
> + for (i = 0; i < elem; i++) { \
> + r = r << 8; \
> + if (index - i >= 0) { \
> + r = r | b->u8[index - i]; \
> + } \
> + } \
> + return r; \
> +}
> +#endif
> +
> +VEXTULX_DO(vextublx, 1)
> +VEXTULX_DO(vextuhlx, 2)
> +VEXTULX_DO(vextuwlx, 4)
> +#undef VEXTULX_DO
Ew.
This should be one 128-bit shift and one and.
Since the shift amount is a multiple of 8, the 128-bit shift for vextub[lr]x
does not need to cross a double-word boundary, and so can be decomposed into
one 64-bit shift of (count & 64 ? hi : lo).
For vextu[hw]lr]x, you'd need to do the whole left-shift, right-shift, or thing.
But still, fantastically better than a loop.
r~
- [Qemu-ppc] [PATCH 0/6] POWER9 TCG enablement - part5, Rajalakshmi Srinivasaraghavan, 2016/09/28
- [Qemu-ppc] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions, Rajalakshmi Srinivasaraghavan, 2016/09/28
- Re: [Qemu-ppc] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions, Richard Henderson, 2016/09/28
- Re: [Qemu-ppc] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions, David Gibson, 2016/09/28
- Re: [Qemu-ppc] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions, Richard Henderson, 2016/09/29
- Re: [Qemu-ppc] [PATCH 1/6] target-ppc: add vmul10[u, eu, cu, ecu]q instructions, David Gibson, 2016/09/29
- [Qemu-ppc] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions, Rajalakshmi Srinivasaraghavan, 2016/09/28
- Re: [Qemu-ppc] [PATCH 2/6] target-ppc: add vextu[bhw]lx instructions,
Richard Henderson <=
- [Qemu-ppc] [PATCH 4/6] target-ppc: fix invalid mask - cmpl, bctar, Rajalakshmi Srinivasaraghavan, 2016/09/28
- [Qemu-ppc] [PATCH 3/6] target-ppc: add vextu[bhw]rx instructions, Rajalakshmi Srinivasaraghavan, 2016/09/28
- [Qemu-ppc] [PATCH 5/6] target-ppc: add vector compare not equal instructions, Rajalakshmi Srinivasaraghavan, 2016/09/28
- [Qemu-ppc] [PATCH 6/6] target-ppc: add vclzlsbb/vctzlsbb instructions, Rajalakshmi Srinivasaraghavan, 2016/09/28