[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PATCH V2 07/10] target/ppc: Flush TLB on write to PIDR
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [PATCH V2 07/10] target/ppc: Flush TLB on write to PIDR |
Date: |
Wed, 1 Mar 2017 18:12:58 +1100 |
The PIDR (process id register) is used to store the id of the currently
running process, which is used to select the process table entry used to
perform address translation. This means that when we write to this register
all the translations in the TLB become outdated as they are for a
previously running process. Thus when this register is written to we need
to invalidate the TLB entries to ensure stale entries aren't used to
to perform translation for the new process, which would result in at best
segfaults or alternatively just random memory being accessed.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
---
target/ppc/helper.h | 1 +
target/ppc/misc_helper.c | 8 ++++++++
target/ppc/translate_init.c | 8 +++++++-
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6d77661..bb6a94a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -709,6 +709,7 @@ DEF_HELPER_FLAGS_1(load_601_rtcu, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_1(load_purr, TCG_CALL_NO_RWG, tl, env)
#endif
DEF_HELPER_2(store_sdr1, void, env, tl)
+DEF_HELPER_2(store_pidr, void, env, tl)
DEF_HELPER_FLAGS_2(store_tbl, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_tbu, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_atbl, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index fa573dd..0e42178 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -88,6 +88,14 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
}
}
+void helper_store_pidr(CPUPPCState *env, target_ulong val)
+{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
+ env->spr[SPR_BOOKS_PID] = val;
+ tlb_flush(CPU(cpu));
+}
+
void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
{
target_ulong hid0;
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index b2dc452..d8bb6ac 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -395,6 +395,12 @@ static void spr_write_sdr1 (DisasContext *ctx, int sprn,
int gprn)
gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
}
+/* PIDR */
+static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
+}
+
/* 64 bits PowerPC specific SPRs */
#if defined(TARGET_PPC64)
static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
@@ -8201,7 +8207,7 @@ static void gen_spr_power8_book4(CPUPPCState *env)
KVM_REG_PPC_ACOP, 0);
spr_register_kvm(env, SPR_BOOKS_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_pidr,
KVM_REG_PPC_PID, 0);
spr_register_kvm(env, SPR_WORT, "WORT",
SPR_NOACCESS, SPR_NOACCESS,
--
2.5.5
- Re: [Qemu-ppc] [PATCH V2 01/10] target/ppc: Add Instruction Authority Mask Register Check, (continued)
- [Qemu-ppc] [PATCH V2 02/10] target/ppc: Add execute permission checking to access authority check, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V2 03/10] target/ppc: Move no-execute and guarded page checking into new function, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V2 04/10] target/ppc: Rework hash mmu page fault code and add defines for clarity, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V2 05/10] target/ppc: Add ibm, processor-radix-AP-encodings for TCG, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V2 06/10] target/ppc: Add POWER9/ISAv3.00 to compat_table, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V2 07/10] target/ppc: Flush TLB on write to PIDR,
Suraj Jitindar Singh <=
- [Qemu-ppc] [PATCH V2 08/10] target/ppc: Adapt tlbie[l] for ISAv3.00 Support, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V2 09/10] target/ppc: Implement ISA V3.00 radix page fault handler, Suraj Jitindar Singh, 2017/03/01
- [Qemu-ppc] [PATCH V2 10/10] target/ppc: Enable RADIX for pseries TCG guest, Suraj Jitindar Singh, 2017/03/01