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[Qemu-ppc] [PATCH v5 8/9] ppc/pnv: add a helper to calculate MMIO addres
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v5 8/9] ppc/pnv: add a helper to calculate MMIO addresses registers |
Date: |
Mon, 3 Apr 2017 09:46:04 +0200 |
Some controllers (ICP, PSI) have a base register address which is
calculated using the chip id.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
---
include/hw/ppc/pnv.h | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index df98a72006e4..5693ba181d24 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -91,14 +91,24 @@ typedef struct PnvChipClass {
OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
/*
- * This generates a HW chip id depending on an index:
+ * This generates a HW chip id depending on an index, as found on a
+ * two socket system with dual chip modules :
*
* 0x0, 0x1, 0x10, 0x11
*
* 4 chips should be the maximum
+ *
+ * TODO: use a machine property to define the chip ids
*/
#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
+/*
+ * Converts back a HW chip id to an index. This is useful to calculate
+ * the MMIO addresses of some controllers which depend on the chip id.
+ */
+#define PNV_CHIP_INDEX(chip) \
+ (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
+
#define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv")
#define POWERNV_MACHINE(obj) \
OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE)
--
2.7.4
- [Qemu-ppc] [PATCH v5 0/9] ppc/pnv: interrupt controller (POWER8), Cédric Le Goater, 2017/04/03
- [Qemu-ppc] [PATCH v5 1/9] spapr: move the IRQ server number mapping under the machine, Cédric Le Goater, 2017/04/03
- [Qemu-ppc] [PATCH v5 2/9] spapr: allocate the ICPState object from under sPAPRCPUCore, Cédric Le Goater, 2017/04/03
- [Qemu-ppc] [PATCH v5 3/9] ppc/xics: add a realize() handler to ICPStateClass, Cédric Le Goater, 2017/04/03
- [Qemu-ppc] [PATCH v5 4/9] ppc/pnv: add a PnvICPState object, Cédric Le Goater, 2017/04/03
- [Qemu-ppc] [PATCH v5 5/9] ppc/pnv: extend the machine with a XICSFabric interface, Cédric Le Goater, 2017/04/03
- [Qemu-ppc] [PATCH v5 7/9] ppc/pnv: create the ICP object under PnvCore, Cédric Le Goater, 2017/04/03
- [Qemu-ppc] [PATCH v5 6/9] ppc/pnv: extend the machine with a InterruptStatsProvider interface, Cédric Le Goater, 2017/04/03
- [Qemu-ppc] [PATCH v5 8/9] ppc/pnv: add a helper to calculate MMIO addresses registers,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v5 9/9] ppc/pnv: add memory regions for the ICP registers, Cédric Le Goater, 2017/04/03
- Re: [Qemu-ppc] [PATCH v5 0/9] ppc/pnv: interrupt controller (POWER8), David Gibson, 2017/04/05