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Re: [Qemu-ppc] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the


From: David Gibson
Subject: Re: [Qemu-ppc] [RFC PATCH 04/26] ppc/xive: introduce a skeleton for the XIVE interrupt controller model
Date: Fri, 21 Jul 2017 17:50:15 +1000
User-agent: Mutt/1.8.3 (2017-05-23)

On Wed, Jul 19, 2017 at 02:02:18PM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2017-07-19 at 13:08 +1000, David Gibson wrote:
> > 
> > I'm somewhat uncomfortable with an irq allocater here in the intc
> > code.  As a rule, irq allocation is the responsibility of the machine,
> > not any sub-component.  Furthermore, it should allocate in a way which
> > is repeatable, since they need to stay stable across reboots and
> > migrations.
> > 
> > And, yes, we have an allocator of sorts in XICS - it has caused a
> > number of problems in the past.
> 
> So....
> 
> For a bare metal model (which we don't have yet) of XIVE, the IRQ
> numbering is entirely an artifact of how the HW is configured. There
> should thus be no interrupt numbers visible to qemu.

Uh.. I don't entirely follow.  Do you mean that during boot the guest
programs the irq numbers into the various components?

In that case this allocator stuff definitely doesn't belong on the
xive code.

> For a PAPR model things are a bit different, but if we want to
> maximize code re-use between the two, we probably need to make sure
> the interrupts "allocated" by the machine for XIVE can be represented
> by the HW model.
> 
> That means:
> 
>  - Each chip has a range (high bits are the block ID, which maps to a
> chip, low bits, around 512K to 1M interrupts is the per-chip space).
> 
>  - Interrupts 0...N of that range (N depends on how much backing
> memory and MMIO space is provisioned for each chip) are "generic IPIs"
> which are somewhat generic interrupt source that can be triggered with
> an MMIO store and routed to any target. Those are used in PAPR for
> things like IPIs and some type of accelerator interrupts.
> 
>  - Portions of that range (which may or may not overlap the 0...N
> above, if they do they "shadow" the generic interrupts) can be
> configured to be the HW sources from the various PCIe bridges and
> the PSI controller.

Err.. I'm confused how this not sure this relates to spapr.  There are
no chips or PSI there, and the PCI bridges aren't really the same
thing.

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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