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[Qemu-ppc] [PATCH v2 13/19] spapr: add device tree support for the XIVE
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v2 13/19] spapr: add device tree support for the XIVE interrupt mode |
Date: |
Sat, 9 Dec 2017 09:43:32 +0100 |
The XIVE interface for the guest is described in the device tree under
the "interrupt-controller" node. A couple of new properties are
specific to XIVE :
- "reg"
contains the base address and size of the thread interrupt
managnement areas (TIMA), also called rings, for the User level and
for the Guest OS level. Only the Guest OS level is taken into
account today.
- "ibm,xive-eq-sizes"
the size of the event queues. One cell per size supported, contains
log2 of size, in ascending order.
- "ibm,xive-lisn-ranges"
the IRQ interrupt number ranges assigned to the guest for the IPIs.
and also under the root node :
- "ibm,plat-res-int-priorities"
contains a list of priorities that the hypervisor has reserved for
its own use. OPAL uses the priority 7 queue to automatically
escalate interrupts for all other queues (DD2.X POWER9). So only
priorities [0..6] are allowed for the guest.
When the XIVE exploitation interrupt mode is activated after the CAS
negotiation, the machine will perform a reboot to rebuild the device
tree.
Signed-off-by: Cédric Le Goater <address@hidden>
---
Changes since v1:
- added a unit id to the nodename
- added properties for the LSIs
- simplified the array for the "ibm,plat-res-int-priorities" property
- renamed to spapr_dt_xive()
hw/intc/spapr_xive_hcall.c | 64 +++++++++++++++++++++++++++++++++++++++++++++
hw/ppc/spapr.c | 7 ++++-
hw/ppc/spapr_hcall.c | 6 +++++
include/hw/ppc/spapr_xive.h | 2 ++
4 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/hw/intc/spapr_xive_hcall.c b/hw/intc/spapr_xive_hcall.c
index 86dec6c02401..8aa2fb8a32d1 100644
--- a/hw/intc/spapr_xive_hcall.c
+++ b/hw/intc/spapr_xive_hcall.c
@@ -857,3 +857,67 @@ void spapr_xive_hcall_init(sPAPRMachineState *spapr)
spapr_register_hypercall(H_INT_SYNC, h_int_sync);
spapr_register_hypercall(H_INT_RESET, h_int_reset);
}
+
+void spapr_dt_xive(sPAPRMachineState *spapr, int nr_servers,
+ void *fdt, uint32_t phandle)
+{
+ sPAPRXive *xive = spapr->xive;
+ int node;
+ uint64_t timas[2 * 2];
+ /* Interrupt number ranges for the IPIs */
+ uint32_t lisn_ranges[] = {
+ cpu_to_be32(0),
+ cpu_to_be32(nr_servers),
+ };
+ uint32_t eq_sizes[] = {
+ cpu_to_be32(12), /* 4K */
+ cpu_to_be32(16), /* 64K */
+ cpu_to_be32(21), /* 2M */
+ cpu_to_be32(24), /* 16M */
+ };
+ /* The following array is in sync with the 'priority_is_valid'
+ * routine above. Linux is expected to choose priority 6.
+ */
+ uint32_t plat_res_int_priorities[] = {
+ cpu_to_be32(7), /* start */
+ cpu_to_be32(0xf8), /* count */
+ };
+ int i;
+ gchar *nodename;
+
+ /* Thread Interrupt Management Area : User and OS views */
+ for (i = 0; i < 2; i++) {
+ timas[i * 2] = cpu_to_be64(xive->tm_base + i * (1ull << TM_SHIFT));
+ timas[i * 2 + 1] = cpu_to_be64(1ull << TM_SHIFT);
+ }
+
+ nodename = g_strdup_printf("address@hidden" PRIx64, xive->tm_base);
+ _FDT(node = fdt_add_subnode(fdt, 0, nodename));
+ g_free(nodename);
+
+ _FDT(fdt_setprop_string(fdt, node, "device_type", "power-ivpe"));
+ _FDT(fdt_setprop(fdt, node, "reg", timas, sizeof(timas)));
+
+ _FDT(fdt_setprop_string(fdt, node, "compatible", "ibm,power-ivpe"));
+ _FDT(fdt_setprop(fdt, node, "ibm,xive-eq-sizes", eq_sizes,
+ sizeof(eq_sizes)));
+ _FDT(fdt_setprop(fdt, node, "ibm,xive-lisn-ranges", lisn_ranges,
+ sizeof(lisn_ranges)));
+
+ /* For Linux to link the LSIs to the main interrupt controller.
+ * These properties are not in XIVE exploitation mode sPAPR
+ * specs
+ */
+ _FDT(fdt_setprop(fdt, node, "interrupt-controller", NULL, 0));
+ _FDT(fdt_setprop_cell(fdt, node, "#interrupt-cells", 2));
+
+ /* For SLOF */
+ _FDT(fdt_setprop_cell(fdt, node, "linux,phandle", phandle));
+ _FDT(fdt_setprop_cell(fdt, node, "phandle", phandle));
+
+ /* The "ibm,plat-res-int-priorities" property defines the priority
+ * ranges reserved by the hypervisor
+ */
+ _FDT(fdt_setprop(fdt, 0, "ibm,plat-res-int-priorities",
+ plat_res_int_priorities,
sizeof(plat_res_int_priorities)));
+}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 1a71bf613b9e..2e15ee8a9333 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1155,7 +1155,12 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr,
_FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
/* /interrupt controller */
- spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);
+ if (!spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
+ spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP);
+ } else {
+ /* Populate device tree for XIVE */
+ spapr_dt_xive(spapr, xics_max_server_number(), fdt, PHANDLE_XICP);
+ }
ret = spapr_populate_memory(spapr, fdt);
if (ret < 0) {
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index be22a6b2895f..e2a1665beee9 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1646,6 +1646,12 @@ static target_ulong
h_client_architecture_support(PowerPCCPU *cpu,
(spapr_h_cas_compose_response(spapr, args[1], args[2],
ov5_updates) != 0);
}
+
+ /* We need to rebuild the device tree for XIVE, generate a reset */
+ if (!spapr->cas_reboot) {
+ spapr->cas_reboot = spapr_ovec_test(ov5_updates, OV5_XIVE_EXPLOIT);
+ }
+
spapr_ovec_cleanup(ov5_updates);
if (spapr->cas_reboot) {
diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h
index 0385df69b028..8c3b9cb194a9 100644
--- a/include/hw/ppc/spapr_xive.h
+++ b/include/hw/ppc/spapr_xive.h
@@ -63,5 +63,7 @@ void spapr_xive_nvt_pic_print_info(sPAPRXiveNVT *nvt, Monitor
*mon);
typedef struct sPAPRMachineState sPAPRMachineState;
void spapr_xive_hcall_init(sPAPRMachineState *spapr);
+void spapr_dt_xive(sPAPRMachineState *spapr, int nr_servers, void *fdt,
+ uint32_t phandle);
#endif /* PPC_SPAPR_XIVE_H */
--
2.13.6
- Re: [Qemu-ppc] [PATCH v2 03/19] spapr: introduce the XIVE interrupt sources, (continued)
- [Qemu-ppc] [PATCH v2 04/19] spapr: add support for the LSI interrupt sources, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 05/19] spapr: introduce a XIVE interrupt presenter model, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 06/19] spapr: introduce the XIVE Event Queues, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 07/19] spapr: push the XIVE EQ data in OS event queue, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 08/19] spapr: notify the CPU when the XIVE interrupt priority is more privileged, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 09/19] spapr: add support for the SET_OS_PENDING command (XIVE), Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 10/19] spapr: introduce a 'xive_exploitation' boolean to enable XIVE, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 11/19] spapr: add a sPAPRXive object to the machine, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 12/19] spapr: add hcalls support for the XIVE exploitation interrupt mode, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 13/19] spapr: add device tree support for the XIVE interrupt mode,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v2 14/19] spapr: introduce a helper to map the XIVE memory regions, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 15/19] spapr: add XIVE support to spapr_qirq(), Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 16/19] spapr: introduce a spapr_icp_create() helper, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 17/19] spapr: toggle the ICP depending on the selected interrupt mode, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 18/19] spapr: add support to dump XIVE information, Cédric Le Goater, 2017/12/09
- [Qemu-ppc] [PATCH v2 19/19] spapr: advertise XIVE exploitation mode in CAS, Cédric Le Goater, 2017/12/09