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Re: [Qemu-ppc] [PULL 03/30] ppc440: Add emulation of plb-pcix controller

From: BALATON Zoltan
Subject: Re: [Qemu-ppc] [PULL 03/30] ppc440: Add emulation of plb-pcix controller found in some 440 SoCs
Date: Fri, 27 Apr 2018 23:38:44 +0200 (CEST)
User-agent: Alpine 2.21 (BSF 202 2017-01-01)

On Fri, 27 Apr 2018, Peter Maydell wrote:
On 6 March 2018 at 04:01, David Gibson <address@hidden> wrote:
From: BALATON Zoltan <address@hidden>

This is the PCIX controller found in newer 440 core SoCs e.g. the
AMMC 460EX. The device tree refers to this as plb-pcix compared to
the plb-pci controller in older 440 SoCs.

Signed-off-by: BALATON Zoltan <address@hidden>
[dwg: Remove hwaddr from trace-events, that doesn't work with some
 trace backends]
Signed-off-by: David Gibson <address@hidden>

+    case PCIX0_PIM2SAL:
+        s->pim[2].sa &= 0xffffffff00000000ULL;
+        s->pim[2].sa = val;
+        ppc440_pcix_update_pim(s, 2);
+        break;

Coverity (CID1390577) points out that the "s->pim[2].sa = val;"
overwrites the value set by the &= line, making it pointless.
Should this be "|= val" like the other cases in this switch?

Yes this is a typo and I meant |= here like in other cases. I'll send a patch to correct this with the next batch of changes. Thanks for spotting it.


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