Re: [Qemu-ppc] [PATCH v3 9/9] target/ppc: Add missing opcode for icbt on PPC440

[BALATON Zoltan]

On Thu, 14 Jun 2018, David Gibson wrote:
> On Thu, Jun 14, 2018 at 10:03:41AM +0200, BALATON Zoltan wrote:
> > On Thu, 14 Jun 2018, David Gibson wrote:
> > > On Thu, Jun 14, 2018 at 02:17:00AM +0200, BALATON Zoltan wrote:
> >
> > Maybe amend commit message like this:
> >
> > According to PPC440 User Manual
>
> On which page?  Where can I get that manual?

By searching for "PPC440 User Manual"? The one I've found had an opcode 
table at the end in an appendix but I've seen one guest using this machine 
code and get invalid instruction on QEMU while apparently it works on real 
hardware (but I can't test that myself as I don't have real hardware).

Regards,
BALATON Zoltan

> > > > PPC440 has two opcodes for icbt, add the missing one.
> >
> > If you can do this when committing then please feel free to adjust this
> > commit message as necessary, otherwise I'll change it in next iteration.
> >
> > Regards,
> > BALATON Zoltan
> >
> > > A document reference to confim this would be nice.
> > >
> > > > Signed-off-by: BALATON Zoltan <address@hidden>
> > > > ---
> > > >  target/ppc/translate.c | 2 ++
> > > >  1 file changed, 2 insertions(+)
> > > >
> > > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> > > > index 5fe1ba6..3a215a1 100644
> > > > --- a/target/ppc/translate.c
> > > > +++ b/target/ppc/translate.c
> > > > @@ -6707,6 +6707,8 @@ GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
> > > >  GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
> > > >  GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
> > > >                 PPC_BOOKE, PPC2_BOOKE206),
> > > > +GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
> > > > +               PPC_440_SPEC),
> > > >  GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
> > > >  GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
> > > >  GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),