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[Qemu-ppc] [PULL 37/40] spapr: add an extra OV5 field to the sPAPR IRQ b
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 37/40] spapr: add an extra OV5 field to the sPAPR IRQ backend |
Date: |
Fri, 21 Dec 2018 16:46:03 +1100 |
From: Cédric Le Goater <address@hidden>
The interrupt modes supported by the hypervisor are advertised to the
guest with new bits definitions of the option vector 5 of property
"ibm,arch-vec-5-platform-support. The byte 23 bits 0-1 of the OV5 are
defined as follow :
0b00 PAPR 2.7 and earlier (Legacy systems)
0b01 XIVE Exploitation mode only
0b10 Either available
If the client/guest selects the XIVE interrupt mode, it informs the
hypervisor by returning the value 0b01 in byte 23 bits 0-1. A 0b00
value indicates the use of the XICS interrupt mode (Legacy systems).
The sPAPR IRQ backend is extended with these definitions and the
values are directly used to populate the "ibm,arch-vec-5-platform-support"
property. The interrupt mode is advertised under TCG and under KVM.
Although a KVM XIVE device is not yet available, the machine can still
operate with kernel_irqchip=off. However, we apply a restriction on
the CPU which is required to be a POWER9 when a XIVE interrupt
controller is in use.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr.c | 33 ++++++++++++++++++++++++++-------
hw/ppc/spapr_irq.c | 3 +++
include/hw/ppc/spapr.h | 6 ++++++
include/hw/ppc/spapr_irq.h | 1 +
4 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 487f80e940..2f87c8ba19 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1095,15 +1095,19 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr,
void *fdt)
spapr_dt_rtas_tokens(fdt, rtas);
}
-/* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
- * that the guest may request and thus the valid values for bytes 24..26 of
- * option vector 5: */
-static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
+/*
+ * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
+ * and the XIVE features that the guest may request and thus the valid
+ * values for bytes 23..26 of option vector 5:
+ */
+static void spapr_dt_ov5_platform_support(sPAPRMachineState *spapr, void *fdt,
+ int chosen)
{
PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
+ sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
char val[2 * 4] = {
- 23, 0x00, /* Xive mode, filled in below. */
+ 23, smc->irq->ov5, /* Xive mode. */
24, 0x00, /* Hash/Radix, filled in below. */
25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
26, 0x40, /* Radix options: GTSE == yes. */
@@ -1111,7 +1115,11 @@ static void spapr_dt_ov5_platform_support(void *fdt, int
chosen)
if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
first_ppc_cpu->compat_pvr)) {
- /* If we're in a pre POWER9 compat mode then the guest should do hash
*/
+ /*
+ * If we're in a pre POWER9 compat mode then the guest should
+ * do hash and use the legacy interrupt mode
+ */
+ val[1] = 0x00; /* XICS */
val[3] = 0x00; /* Hash */
} else if (kvm_enabled()) {
if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
@@ -1189,7 +1197,7 @@ static void spapr_dt_chosen(sPAPRMachineState *spapr,
void *fdt)
_FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
}
- spapr_dt_ov5_platform_support(fdt, chosen);
+ spapr_dt_ov5_platform_support(spapr, fdt, chosen);
g_free(stdout_path);
g_free(bootlist);
@@ -2624,6 +2632,17 @@ static void spapr_machine_init(MachineState *machine)
/* advertise support for ibm,dyamic-memory-v2 */
spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
+ /* advertise XIVE on POWER9 machines */
+ if (smc->irq->ov5 & SPAPR_OV5_XIVE_EXPLOIT) {
+ if (ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,
+ 0, spapr->max_compat_pvr)) {
+ spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
+ } else {
+ error_report("XIVE-only machines require a POWER9 CPU");
+ exit(1);
+ }
+ }
+
/* init CPUs */
spapr_init_cpus(spapr);
diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
index 9ecbf47329..9e3aa85b6d 100644
--- a/hw/ppc/spapr_irq.c
+++ b/hw/ppc/spapr_irq.c
@@ -216,6 +216,7 @@ static int spapr_irq_post_load_xics(sPAPRMachineState
*spapr, int version_id)
sPAPRIrq spapr_irq_xics = {
.nr_irqs = SPAPR_IRQ_XICS_NR_IRQS,
.nr_msis = SPAPR_IRQ_XICS_NR_MSIS,
+ .ov5 = SPAPR_OV5_XIVE_LEGACY,
.init = spapr_irq_init_xics,
.claim = spapr_irq_claim_xics,
@@ -343,6 +344,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr,
Error **errp)
sPAPRIrq spapr_irq_xive = {
.nr_irqs = SPAPR_IRQ_XIVE_NR_IRQS,
.nr_msis = SPAPR_IRQ_XIVE_NR_MSIS,
+ .ov5 = SPAPR_OV5_XIVE_EXPLOIT,
.init = spapr_irq_init_xive,
.claim = spapr_irq_claim_xive,
@@ -467,6 +469,7 @@ int spapr_irq_find(sPAPRMachineState *spapr, int num, bool
align, Error **errp)
sPAPRIrq spapr_irq_xics_legacy = {
.nr_irqs = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
.nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
+ .ov5 = SPAPR_OV5_XIVE_LEGACY,
.init = spapr_irq_init_xics,
.claim = spapr_irq_claim_xics,
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 6bf028a02f..06765b4e9d 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -824,5 +824,11 @@ int spapr_caps_post_migration(sPAPRMachineState *spapr);
void spapr_check_pagesize(sPAPRMachineState *spapr, hwaddr pagesize,
Error **errp);
+/*
+ * XIVE definitions
+ */
+#define SPAPR_OV5_XIVE_LEGACY 0x0
+#define SPAPR_OV5_XIVE_EXPLOIT 0x40
+#define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */
#endif /* HW_SPAPR_H */
diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h
index 63061a009b..b34d5a0038 100644
--- a/include/hw/ppc/spapr_irq.h
+++ b/include/hw/ppc/spapr_irq.h
@@ -33,6 +33,7 @@ void spapr_irq_msi_reset(sPAPRMachineState *spapr);
typedef struct sPAPRIrq {
uint32_t nr_irqs;
uint32_t nr_msis;
+ uint8_t ov5;
void (*init)(sPAPRMachineState *spapr, Error **errp);
int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp);
--
2.19.2
- [Qemu-ppc] [PULL 27/40] ppc/xive: notify the CPU when the interrupt priority is more privileged, (continued)
- [Qemu-ppc] [PULL 27/40] ppc/xive: notify the CPU when the interrupt priority is more privileged, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 28/40] spapr/xive: introduce a XIVE interrupt controller, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 26/40] ppc/xive: introduce a simplified XIVE presenter, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 30/40] spapr-iommu: Always advertise the maximum possible DMA window size, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 29/40] spapr/xive: use the VCPU id as a NVT identifier, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 33/40] spapr: add device tree support for the XIVE exploitation mode, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 32/40] spapr: add hcalls support for the XIVE exploitation interrupt mode, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 31/40] spapr: introduce a new machine IRQ backend for XIVE, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 36/40] spapr: add a 'reset' method to the sPAPR IRQ backend, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 39/40] spapr: change default CPU type to POWER9, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 37/40] spapr: add an extra OV5 field to the sPAPR IRQ backend,
David Gibson <=
- [Qemu-ppc] [PULL 40/40] MAINTAINERS: PPC: add a XIVE section, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 35/40] spapr: extend the sPAPR IRQ backend for XICS migration, David Gibson, 2018/12/21
- [Qemu-ppc] [PULL 38/40] spapr: introduce an 'ic-mode' machine option, David Gibson, 2018/12/21
- Re: [Qemu-ppc] [PULL 00/40] ppc-for-4.0 queue 20181221, Peter Maydell, 2018/12/21
- Re: [Qemu-ppc] [Qemu-devel] [PULL 00/40] ppc-for-4.0 queue 20181221, no-reply, 2018/12/26