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[Qemu-riscv] [PATCH v1 21/23] tcg: Add RISC-V cpu signal handler
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From: |
Alistair Francis |
|
Subject: |
[Qemu-riscv] [PATCH v1 21/23] tcg: Add RISC-V cpu signal handler |
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Date: |
Wed, 12 Dec 2018 19:46:07 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
accel/tcg/user-exec.c | 75 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index cd75829cf2..941295ea49 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -571,6 +571,81 @@ int cpu_signal_handler(int host_signum, void *pinfo,
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
}
+#elif defined(__riscv)
+
+int cpu_signal_handler(int host_signum, void *pinfo,
+ void *puc)
+{
+ siginfo_t *info = pinfo;
+ ucontext_t *uc = puc;
+ greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
+ uint32_t insn = *(uint32_t *)pc;
+ int is_write = 0;
+
+ /* Detect store by reading the instruction at the program
+ counter. Note: we currently only generate 32-bit
+ instructions so we thus only detect 32-bit stores */
+ switch (((insn >> 0) & 0b11)) {
+ case 3:
+ switch (((insn >> 2) & 0b11111)) {
+ case 8:
+ switch (((insn >> 12) & 0b111)) {
+ case 0: /* sb */
+ case 1: /* sh */
+ case 2: /* sw */
+ case 3: /* sd */
+ case 4: /* sq */
+ is_write = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 9:
+ switch (((insn >> 12) & 0b111)) {
+ case 2: /* fsw */
+ case 3: /* fsd */
+ case 4: /* fsq */
+ is_write = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Check for compressed instructions */
+ switch (((insn >> 13) & 0b111)) {
+ case 7:
+ switch (insn & 0b11) {
+ case 0: /*c.sd */
+ case 2: /* c.sdsp */
+ is_write = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 6:
+ switch (insn & 0b11) {
+ case 0: /* c.sw */
+ case 3: /* c.swsp */
+ is_write = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
+}
+
#else
#error host CPU specific signal handler needed
--
2.19.1
- [Qemu-riscv] [PATCH v1 11/23] riscv: tcg-target: Add the mov and movi instruction, (continued)
- [Qemu-riscv] [PATCH v1 11/23] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 12/23] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 13/23] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 14/23] riscv: tcg-target: Add the add2 and sub2 instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 15/23] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 16/23] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 19/23] riscv: tcg-target: Add the prologue generation and register the JIT, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 21/23] tcg: Add RISC-V cpu signal handler,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 22/23] dias: Add RISC-V support, Alistair Francis, 2018/12/12
- [Qemu-riscv] [PATCH v1 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/12/12
- Re: [Qemu-riscv] [PATCH v1 00/23] Add RISC-V TCG backend support, Richard Henderson, 2018/12/12
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 00/23] Add RISC-V TCG backend support, no-reply, 2018/12/12