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Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_ar
Re: [Qemu-riscv] [Qemu-devel] [PATCH v3 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions
Sat, 12 Jan 2019 08:00:04 +1100
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On 1/12/19 12:10 AM, Bastian Koppelmann wrote:
> On 10/31/18 11:18 PM, Richard Henderson wrote:
>> Surely the shri and sari functions need the same shamt >= TARGET_LONG_BITS
>> check as slli. Otherwise RV32 shri should definitely produce an assert in
>> I did wonder about changing the decode of the shift functions such that only
>> the top two bits of the imm are reserved for secondary parsing of the shift
>> type, and the other 10 bits are passed down into trans_foo. At which point
>> TARGET_LONG_BITS check takes care of other illegalities.
>> Which means that the parsing for slli and slliw are identical, and also that
>> for the far future when RV128 is a thing, we don't have to change the
> I don't quite understand this. Do you want to have one entry in the decode
> for slli and slliw?
> How is the parsing of slli and slliw identical with this change? As far as I
> see it, they are different at least in the opcode.
I meant in the extraction and validation of operands, I think.
I'm not really sure where else I was going with this. It has
been two months and I don't have the decode in front of me.