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Re: [Qemu-riscv] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() dec
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions |
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Date: |
Sun, 20 Jan 2019 12:24:44 +1100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
> static bool trans_slli(DisasContext *ctx, arg_slli *a)
> {
> - gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
> + if (a->rd != 0) {
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
I think the shmat test should be first, so that
slli r0, r1, 99
produces SIGILL instead of translating to a nop.
> static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
> {
> - gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
> - a->shamt | 0x400);
> + TCGv t = tcg_temp_new();
> + gen_get_gpr(t, a->rs1);
> + tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
> + /* sign-extend for W instructions */
> + tcg_gen_ext32s_tl(t, t);
Sign extension of a sign-extracted value?
r~
- [Qemu-riscv] [PATCH v4 30/35] target/riscv: Remove decode_RV32_64G(), (continued)
- [Qemu-riscv] [PATCH v4 30/35] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 14/35] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/18
- Re: [Qemu-riscv] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions,
Richard Henderson <=
[Qemu-riscv] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 09/35] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 29/35] target/riscv: Remove gen_system(), Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Bastian Koppelmann, 2019/01/18