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Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shif
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding |
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Date: |
Mon, 21 Jan 2019 15:22:14 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 |
On 1/21/19 1:10 AM, Bastian Koppelmann wrote:
>
> On 1/20/19 2:43 AM, Richard Henderson wrote:
>> On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
>>> Signed-off-by: Bastian Koppelmann <address@hidden>
>>> Signed-off-by: Peer Adelt <address@hidden>
>>> ---
>>> v3 -> v4:
>>> - refactor tcg_gen_set_cond_tl(TCG_COND_LT,..) into gen_slt function
>>> and reuse gen_arith(..., &gen_slt) for all trans_slt functions.
>>> - Add missing sign extension to trans_srlw/sllw
>>> - Made rs2 == 0 a special case of srlw/sllw
>> Why? It's not like it is a likely case, and it works without.
>
>
> Because you suggested it :) (see
> https://patchwork.kernel.org/patch/10662699/).
> Maybe I misunderstood your comment. If you like I can remove it in the respin.
I meant the register indicated by rs2 containing the value 0,
which you have fixed with the extension.
r~
- [Qemu-riscv] [PATCH v4 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, (continued)
- [Qemu-riscv] [PATCH v4 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 10/35] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 31/35] target/riscv: Convert @cs_2 insns to share translation functions<Paste>, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 30/35] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 14/35] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2019/01/18
- [Qemu-riscv] [PATCH v4 26/35] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 09/35] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 29/35] target/riscv: Remove gen_system(), Bastian Koppelmann, 2019/01/18
[Qemu-riscv] [PATCH v4 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Bastian Koppelmann, 2019/01/18