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[Qemu-riscv] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer t
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From: |
Palmer Dabbelt |
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Subject: |
[Qemu-riscv] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext |
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Date: |
Wed, 13 Feb 2019 07:53:40 -0800 |
From: Bastian Koppelmann <address@hidden>
CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.
Reviewed-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target/riscv/translate.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b7176cbf98e1..9e06eb8c2de5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -54,6 +54,7 @@ typedef struct DisasContext {
to any system register, which includes CSR_FRM, so we do not have
to reset this known value. */
int frm;
+ CPURISCVState *env;
} DisasContext;
/* convert riscv funct3 to qemu memop for load/store */
@@ -2003,7 +2004,7 @@ static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
if (extract32(ctx->opcode, 0, 2) != 3) {
- if (!has_ext(ctx, RVC)) {
+ if (!riscv_has_ext(ctx->env, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
@@ -2058,9 +2059,9 @@ static bool riscv_tr_breakpoint_check(DisasContextBase
*dcbase, CPUState *cpu,
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cpu->env_ptr;
+ ctx->env = cpu->env_ptr;
- ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
+ ctx->opcode = cpu_ldl_code(ctx->env, ctx->base.pc_next);
decode_opc(ctx);
ctx->base.pc_next = ctx->pc_succ_insn;
--
2.18.1
- [Qemu-riscv] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree, (continued)
- [Qemu-riscv] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 15/35] target/riscv: Convert RV64D insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 26/35] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext,
Palmer Dabbelt <=
- [Qemu-riscv] [PATCH v7 28/35] target/riscv: Rename trans_arith to gen_arith, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 31/35] target/riscv: Convert @cs_2 insns to share translation functions, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 14/35] target/riscv: Convert RV32D insns to decodetree, Palmer Dabbelt, 2019/02/13