Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURIS

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Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURIS

From:	Bastian Koppelmann
Subject:	Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext
Date:	Wed, 13 Feb 2019 17:18:00 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0


On 2/13/19 4:53 PM, Palmer Dabbelt wrote:

From: Bastian Koppelmann <address@hidden>

CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.

Reviewed-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
---
  target/riscv/translate.c | 7 ++++---
  1 file changed, 4 insertions(+), 3 deletions(-)

We can drop this patch as you pull request already fixes this. (seehttps://patchwork.kernel.org/patch/10794241/)


Cheers,

Bastian

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[Qemu-riscv] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store(), (continued)
- [Qemu-riscv] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch(), Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/02/15
- [Qemu-riscv] [PATCH v7 15/35] target/riscv: Convert RV64D insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 26/35] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 12/35] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2019/02/15
- [Qemu-riscv] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Bastian Koppelmann <=
- [Qemu-riscv] [PATCH v7 28/35] target/riscv: Rename trans_arith to gen_arith, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/02/13
  - Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 16/35] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2019/02/15
- [Qemu-riscv] [PATCH v7 31/35] target/riscv: Convert @cs_2 insns to share translation functions, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 27/35] target/riscv: Remove manual decoding of RV32/64M insn, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 14/35] target/riscv: Convert RV32D insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 18/35] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13

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