Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree

[no-reply]

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/address@hidden -> patchew/address@hidden
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for 
path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) 
registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 
'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 
'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered 
for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) 
registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) 
registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for 
path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) 
registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for 
path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for 
path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for 
path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) 
registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' 
(https://github.com/cota/berkeley-softfloat-3) registered for path 
'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' 
(https://github.com/cota/berkeley-testfloat-3) registered for path 
'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out 
'22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 
'90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 
'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 
'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 
'441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 
'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 
'51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 
'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out 
'1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 
'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 
'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 
'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out 
'60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 
'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out 
'5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
1c6bdfe target/riscv: Remaining rvc insn reuse 32 bit translators
d8ca8fc target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
c43a08f target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
7658d55 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
12beb8b target/riscv: Convert @cs_2 insns to share translation functions
f2a8173 target/riscv: Remove decode_RV32_64G()
8894e2f target/riscv: Remove gen_system()
2e8f564 target/riscv: Rename trans_arith to gen_arith
d324cc4 target/riscv: Remove manual decoding of RV32/64M insn
8dd0068 target/riscv: Remove shift and slt insn manual decoding
9b92836 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
d6590d1 target/riscv: Move gen_arith_imm() decoding into trans_* functions
47b4071 target/riscv: Remove manual decoding from gen_store()
e8e1df3 target/riscv: Remove manual decoding from gen_load()
1a7dbe9 target/riscv: Remove manual decoding from gen_branch()
dfc0199 target/riscv: Remove gen_jalr()
19a6562 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
39bd800 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a6d286f target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8a6d6a3 target/riscv: Convert RV priv insns to decodetree
21a5523 target/riscv: Convert RV64D insns to decodetree
4be6a7c target/riscv: Convert RV32D insns to decodetree
d78760d target/riscv: Convert RV64F insns to decodetree
8597684 target/riscv: Convert RV32F insns to decodetree
3984402 target/riscv: Convert RV64A insns to decodetree
6991b83 target/riscv: Convert RV32A insns to decodetree
29a6d49 target/riscv: Convert RVXM insns to decodetree
4fa5d7b target/riscv: Convert RVXI csr insns to decodetree
ea57911 target/riscv: Convert RVXI fence insns to decodetree
3db0b3f target/riscv: Convert RVXI arithmetic insns to decodetree
e4fa6cd target/riscv: Convert RV64I load/store insns to decodetree
26069dc target/riscv: Convert RV32I load/store insns to decodetree
f70fb7c target/riscv: Convert RVXI branch insns to decodetree
82f3450 target/riscv: Activate decodetree and implemnt LUI & AUIPC
6fc1324 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 6fc132406dff (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 82f3450ac738 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1885:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit f70fb7c7ddae (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 26069dcf702a (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit e4fa6cdb3991 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 3db0b3f2090b (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit ea579111ef40 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 4fa5d7b56e95 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit 29a6d4935194 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 6991b839b1a9 (target/riscv: Convert RV32A insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 39844028ac4e (target/riscv: Convert RV64A insns to 
decodetree)
12/35 Checking commit 8597684b432c (target/riscv: Convert RV32F insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78: 
new file mode 100644

total: 0 errors, 1 warnings, 416 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit d78760da752f (target/riscv: Convert RV64F insns to 
decodetree)
14/35 Checking commit 4be6a7c28c64 (target/riscv: Convert RV32D insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51: 
new file mode 100644

total: 0 errors, 1 warnings, 373 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 21a55239cac5 (target/riscv: Convert RV64D insns to 
decodetree)
16/35 Checking commit 8a6d6a3134dd (target/riscv: Convert RV priv insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit a6d286ffb24c (target/riscv: Convert quadrant 0 of RVXC 
insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:1067:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit 39bd80093d18 (target/riscv: Convert quadrant 1 of RVXC 
insns to decodetree)
19/35 Checking commit 19a6562703b6 (target/riscv: Convert quadrant 2 of RVXC 
insns to decodetree)
20/35 Checking commit dfc0199b2cc3 (target/riscv: Remove gen_jalr())
21/35 Checking commit 1a7dbe9e0633 (target/riscv: Remove manual decoding from 
gen_branch())
22/35 Checking commit e8e1df3a570e (target/riscv: Remove manual decoding from 
gen_load())
23/35 Checking commit 47b407149e90 (target/riscv: Remove manual decoding from 
gen_store())
24/35 Checking commit d6590d16d7a6 (target/riscv: Move gen_arith_imm() decoding 
into trans_* functions)
25/35 Checking commit 9b9283643e0b (target/riscv: make ADD/SUB/OR/XOR/AND insn 
use arg lists)
26/35 Checking commit 8dd0068daa6a (target/riscv: Remove shift and slt insn 
manual decoding)
27/35 Checking commit d324cc4619d9 (target/riscv: Remove manual decoding of 
RV32/64M insn)
28/35 Checking commit 2e8f56430485 (target/riscv: Rename trans_arith to 
gen_arith)
29/35 Checking commit 8894e2fe73ea (target/riscv: Remove gen_system())
30/35 Checking commit f2a81733046c (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 12beb8bb47f9 (target/riscv: Convert @cs_2 insns to share 
translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:543:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit 7658d5513c89 (target/riscv: Convert @cl_d, @cl_w, @cs_d, 
@cs_w insns)
33/35 Checking commit c43a08f0e7de (target/riscv: Splice fsw_sd and flw_ld for 
riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 309 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit d8ca8fce4ad7 (target/riscv: Splice remaining compressed 
insn pairs for riscv32 vs riscv64)
35/35 Checking commit 1c6bdfe98959 (target/riscv: Remaining rvc insn reuse 32 
bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
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