Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree

[no-reply]

Patchew URL: https://patchew.org/QEMU/address@hidden/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   81dbcfa..1e36232  master     -> master
 - [tag update]      patchew/address@hidden -> patchew/address@hidden
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for 
path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) 
registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 
'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 
'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered 
for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) 
registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) 
registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for 
path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) 
registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for 
path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for 
path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for 
path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) 
registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' 
(https://github.com/cota/berkeley-softfloat-3) registered for path 
'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' 
(https://github.com/cota/berkeley-testfloat-3) registered for path 
'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out 
'22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 
'90c488d5f4a407342247b9ea869df1c2d9c8e266'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 
'a5b428e1c1eae703bdd62a3f527223c291ee3fdc'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 
'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 
'3464681b2b5983df80086a40179d324102347da3'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 
'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 
'51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 
'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out 
'1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 
'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 
'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 
'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out 
'60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 
'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out 
'5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
159ce3d target/riscv: Remaining rvc insn reuse 32 bit translators
b9c5f05 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
f121eb7 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
ea8488d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9f90e41 target/riscv: Convert @cs_2 insns to share translation functions
547089b target/riscv: Remove decode_RV32_64G()
ed71f5d target/riscv: Remove gen_system()
5bd06b3 target/riscv: Rename trans_arith to gen_arith
67bcaf7 target/riscv: Remove manual decoding of RV32/64M insn
1db291f target/riscv: Remove shift and slt insn manual decoding
9e2443a target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
9470964 target/riscv: Move gen_arith_imm() decoding into trans_* functions
8996df7 target/riscv: Remove manual decoding from gen_store()
f6544b5 target/riscv: Remove manual decoding from gen_load()
95d0aec target/riscv: Remove manual decoding from gen_branch()
bca491d target/riscv: Remove gen_jalr()
aa2300c target/riscv: Convert quadrant 2 of RVXC insns to decodetree
606ad19 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a0e7a31 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
1a076e5 target/riscv: Convert RV priv insns to decodetree
c474628 target/riscv: Convert RV64D insns to decodetree
387a97f target/riscv: Convert RV32D insns to decodetree
13cc6db target/riscv: Convert RV64F insns to decodetree
31c239b target/riscv: Convert RV32F insns to decodetree
991c4a3 target/riscv: Convert RV64A insns to decodetree
ba101b5 target/riscv: Convert RV32A insns to decodetree
86ecfc5 target/riscv: Convert RVXM insns to decodetree
a9ac09a target/riscv: Convert RVXI csr insns to decodetree
476f9b2 target/riscv: Convert RVXI fence insns to decodetree
b90ac58 target/riscv: Convert RVXI arithmetic insns to decodetree
795f3b5 target/riscv: Convert RV64I load/store insns to decodetree
bdaaf05 target/riscv: Convert RV32I load/store insns to decodetree
e3a8765 target/riscv: Convert RVXI branch insns to decodetree
af57dee target/riscv: Activate decodetree and implemnt LUI & AUIPC
2026d9d target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 2026d9d7cd47 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit af57dee3cb1f (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1885:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit e3a8765ce0f3 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit bdaaf05af449 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 795f3b5f6b05 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit b90ac589471d (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 476f9b2401c3 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit a9ac09a20be5 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit 86ecfc5a0e78 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit ba101b56105e (target/riscv: Convert RV32A insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit 991c4a31fd9a (target/riscv: Convert RV64A insns to 
decodetree)
12/35 Checking commit 31c239b6b03e (target/riscv: Convert RV32F insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78: 
new file mode 100644

total: 0 errors, 1 warnings, 416 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 13cc6dbc4dd5 (target/riscv: Convert RV64F insns to 
decodetree)
14/35 Checking commit 387a97fad262 (target/riscv: Convert RV32D insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51: 
new file mode 100644

total: 0 errors, 1 warnings, 373 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit c4746280227f (target/riscv: Convert RV64D insns to 
decodetree)
16/35 Checking commit 1a076e50a0e1 (target/riscv: Convert RV priv insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit a0e7a318794d (target/riscv: Convert quadrant 0 of RVXC 
insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31: 
new file mode 100644

ERROR: externs should be avoided in .c files
#246: FILE: target/riscv/translate.c:1067:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit 606ad192b60a (target/riscv: Convert quadrant 1 of RVXC 
insns to decodetree)
19/35 Checking commit aa2300cc7ea8 (target/riscv: Convert quadrant 2 of RVXC 
insns to decodetree)
20/35 Checking commit bca491d572b2 (target/riscv: Remove gen_jalr())
21/35 Checking commit 95d0aec06f1c (target/riscv: Remove manual decoding from 
gen_branch())
22/35 Checking commit f6544b5016e9 (target/riscv: Remove manual decoding from 
gen_load())
23/35 Checking commit 8996df716183 (target/riscv: Remove manual decoding from 
gen_store())
24/35 Checking commit 947096487916 (target/riscv: Move gen_arith_imm() decoding 
into trans_* functions)
25/35 Checking commit 9e2443a1f5c9 (target/riscv: make ADD/SUB/OR/XOR/AND insn 
use arg lists)
26/35 Checking commit 1db291fda8f0 (target/riscv: Remove shift and slt insn 
manual decoding)
27/35 Checking commit 67bcaf79f6e5 (target/riscv: Remove manual decoding of 
RV32/64M insn)
28/35 Checking commit 5bd06b38b3eb (target/riscv: Rename trans_arith to 
gen_arith)
29/35 Checking commit ed71f5d6bbbc (target/riscv: Remove gen_system())
30/35 Checking commit 547089b5b669 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 9f90e41eee6d (target/riscv: Convert @cs_2 insns to share 
translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42: 
new file mode 100644

ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:543:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit ea8488d10a09 (target/riscv: Convert @cl_d, @cl_w, @cs_d, 
@cs_w insns)
33/35 Checking commit f121eb761c43 (target/riscv: Splice fsw_sd and flw_ld for 
riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 309 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit b9c5f05eaba7 (target/riscv: Splice remaining compressed 
insn pairs for riscv32 vs riscv64)
35/35 Checking commit 159ce3d78550 (target/riscv: Remaining rvc insn reuse 32 
bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
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