Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree

[Alistair Francis]

On Fri, Feb 22, 2019 at 6:31 AM Bastian Koppelmann
<address@hidden> wrote:
>
> Hi,
>
> this patchset converts the RISC-V decoder to decodetree in four major steps:
>
> 1) Convert 32-bit instructions to decodetree [Patch 1-15]:
>     Many of the gen_* functions are called by the decode functions for 16-bit
>     and 32-bit functions. If we move translation code from the gen_*
>     functions to the generated trans_* functions of decode-tree, we get a lot 
> of
>     duplication. Therefore, we mostly generate calls to the old gen_* function
>     which are properly replaced after step 2).
>
>     Each of the trans_ functions are grouped into files corresponding to their
>     ISA extension, e.g. addi which is in RV32I is translated in the file
>     'trans_rvi.inc.c'.
>
> 2) Convert 16-bit instructions to decodetree [Patch 16-18]:
>     All 16 bit instructions have a direct mapping to a 32 bit instruction. 
> Thus,
>     we convert the arguments in the 16 bit trans_ function to the arguments of
>     the corresponding 32 bit instruction and call the 32 bit trans_ function.
>
> 3) Remove old manual decoding in gen_* function [Patch 19-29]:
>     this move all manual translation code into the trans_* instructions of
>     decode tree, such that we can remove the old decode_* functions.
>
> 4) Simplify RVC by reusing as much as possible from the RVG decoder as 
> suggested
>    by Richard. [Patch 30-34]
>
> full tree available at
> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v8
>
> Cheers,
> Bastian

Tested-by: Alistair Francis <address@hidden>

I haven't run any strenuous tests, but it boots 32 and 64-bit
Linux/openSBI with no issues.

Alistair

>
> v7 -> v8:
>     - add REQUIRE_EXT macro
>     - add missing RVM checks
>     - add missing RVA checks
>     - add missing RVF checks
>     - add missing RVF checks
>     - add missing RVD checks
>     - add missing RVD checks
>     - riscv_has_ext -> has_ext
>     - env->ctx->priv_version -> ctx->priv_version
>     - fixed wrongly inserted #ifdef TARGET_RISCV64 that lead to a compile 
> error
>
>
> Bastian Koppelmann (34):
>   target/riscv: Activate decodetree and implemnt LUI & AUIPC
>   target/riscv: Convert RVXI branch insns to decodetree
>   target/riscv: Convert RV32I load/store insns to decodetree
>   target/riscv: Convert RV64I load/store insns to decodetree
>   target/riscv: Convert RVXI arithmetic insns to decodetree
>   target/riscv: Convert RVXI fence insns to decodetree
>   target/riscv: Convert RVXI csr insns to decodetree
>   target/riscv: Convert RVXM insns to decodetree
>   target/riscv: Convert RV32A insns to decodetree
>   target/riscv: Convert RV64A insns to decodetree
>   target/riscv: Convert RV32F insns to decodetree
>   target/riscv: Convert RV64F insns to decodetree
>   target/riscv: Convert RV32D insns to decodetree
>   target/riscv: Convert RV64D insns to decodetree
>   target/riscv: Convert RV priv insns to decodetree
>   target/riscv: Convert quadrant 0 of RVXC insns to decodetree
>   target/riscv: Convert quadrant 1 of RVXC insns to decodetree
>   target/riscv: Convert quadrant 2 of RVXC insns to decodetree
>   target/riscv: Remove gen_jalr()
>   target/riscv: Remove manual decoding from gen_branch()
>   target/riscv: Remove manual decoding from gen_load()
>   target/riscv: Remove manual decoding from gen_store()
>   target/riscv: Move gen_arith_imm() decoding into trans_* functions
>   target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
>   target/riscv: Remove shift and slt insn manual decoding
>   target/riscv: Remove manual decoding of RV32/64M insn
>   target/riscv: Rename trans_arith to gen_arith
>   target/riscv: Remove gen_system()
>   target/riscv: Remove decode_RV32_64G()
>   target/riscv: Convert @cs_2 insns to share translation functions
>   target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
>   target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
>   target/riscv: Splice remaining compressed insn pairs for riscv32 vs
>     riscv64
>   target/riscv: Remaining rvc insn reuse 32 bit translators
>
>  target/riscv/Makefile.objs                    |   22 +
>  target/riscv/insn16-32.decode                 |   31 +
>  target/riscv/insn16-64.decode                 |   33 +
>  target/riscv/insn16.decode                    |  114 +
>  target/riscv/insn32-64.decode                 |   72 +
>  target/riscv/insn32.decode                    |  203 ++
>  .../riscv/insn_trans/trans_privileged.inc.c   |  110 +
>  target/riscv/insn_trans/trans_rva.inc.c       |  218 ++
>  target/riscv/insn_trans/trans_rvc.inc.c       |  149 ++
>  target/riscv/insn_trans/trans_rvd.inc.c       |  442 ++++
>  target/riscv/insn_trans/trans_rvf.inc.c       |  439 ++++
>  target/riscv/insn_trans/trans_rvi.inc.c       |  568 +++++
>  target/riscv/insn_trans/trans_rvm.inc.c       |  120 +
>  target/riscv/translate.c                      | 1948 ++---------------
>  14 files changed, 2740 insertions(+), 1729 deletions(-)
>  create mode 100644 target/riscv/insn16-32.decode
>  create mode 100644 target/riscv/insn16-64.decode
>  create mode 100644 target/riscv/insn16.decode
>  create mode 100644 target/riscv/insn32-64.decode
>  create mode 100644 target/riscv/insn32.decode
>  create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
>
> --
> 2.20.1
>
>