|Subject:||Re: [Simulavr-devel] Trouble building master branch|
|Date:||Fri, 16 Apr 2010 21:41:55 +0200|
|User-agent:||Mozilla-Thunderbird 22.214.171.124 (X11/20090707)|
And yet another way would be to use the verilog interface and connect your AVRs in Verilog. If you have other surrounding logic, this can also be modeled. In the examples/verilog directory, there is an example of software based single-pin protocol (thus even covering bidirectional PIN usage from verilog). The verilog doesn't consist of so much more than connecting two devices and starting the simulation, so it is somewhat similar to your case.Next step for me will be in a few days to try to have simulavr run two ATmega32 communicating through an SPI link. From what I read in the PDF, that should be possible, am I right ?It's possible, but only with a little bit work. You have to use TCL interface or python interface for that. I've made this with python interface as an example and test, how it could work. But this dosn't work together with gdb. Mostly I don't use gdb, I prefer writing unit tests for development.
Best regards, Onno
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