[Simulavr-devel] spi bug

[zhengxiangwei]

Hi, everyone    I was test two atmega128 spi communication. I find one bug that 
is SPI fails in the followingseting    CPOL=0,CPHA=0,SPI2X=0, SPR1=0,SPR2=0(SCK 
frequency= fosc/4) or 
CPOL=0,CPHA=0,SPI2X=1, SPR1=0,SPR2=0 
(SCK frequency= fosc/2).   The detail reason is master cannot receive the first 
bit slave send.
Also, I do not understand the algorithm of slave part. In slave part        if 
(bitcnt==8) {
      bitcnt=0;
      finished=false;
      shift_in=0;
      oldsck=SCK;
        } else {
      /* Set initial bit for CPHA==0 */
      if (!(spcr&CPHA)) {
            txbit(bitpos);              
      }
  thus if bitcnt !=8, CPHA!=1, txbit will be launched every cup cycle. It is 
totally different from hardware spi.

If anyone has some explanation about this bug, please let me know.
Thank you

 =================================
Xiangwei Zheng
Research Assistant
ECE Department, Virginia Tech
Office: Durham Hall 377
Tel: 540-553-6235