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qemu-riscv (date)
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Last Modified: Mon Jan 31 2022 23:40:43 -0500
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January 31, 2022
Re: [PATCH 0/2] RISC-V: Correctly generate store/amo faults
,
Alistair Francis
,
23:40
Re: [PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Alistair Francis
,
22:35
Re: [PATCH v7 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Alistair Francis
,
22:31
Re: [RFC PATCH] hw/intc: Make RISC-V ACLINT mtime MMIO register writable
,
Alistair Francis
,
21:34
Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
Atish Kumar Patra
,
15:06
Re: [RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
,
Alistair Francis
,
01:34
January 28, 2022
Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
angell1518
,
21:06
Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
Atish Patra
,
20:29
Re: [RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops.
,
Atish Kumar Patra
,
19:52
Re: [RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
,
Atish Kumar Patra
,
19:52
[PATCH v5 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
08:18
[PATCH v5 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
08:18
[PATCH v5 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Weiwei Li
,
08:17
[PATCH v5 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
08:17
[PATCH v5 5/6] target/riscv: add support for zhinx/zhinxmin
,
Weiwei Li
,
08:17
[PATCH v5 0/6] support subsets of Float-Point in Integer Registers extensions
,
Weiwei Li
,
08:17
[PATCH v5 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Weiwei Li
,
08:17
[PATCH v7 0/5] support subsets of virtual memory extension
,
Weiwei Li
,
03:55
[PATCH v7 4/5] target/riscv: add support for svinval extension
,
Weiwei Li
,
03:55
[PATCH v7 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
03:55
[PATCH v7 3/5] target/riscv: add support for svnapot extension
,
Weiwei Li
,
03:55
[PATCH v7 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
03:55
[PATCH v7 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
03:55
Re: [PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
02:38
Re: [PATCH v4 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
02:37
Re: [PATCH v4 3/6] target/riscv: add support for zfinx
,
Alistair Francis
,
01:10
Re: [PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Alistair Francis
,
00:40
Re: [PATCH v4 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Alistair Francis
,
00:37
Re: [PATCH v4 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Alistair Francis
,
00:25
Re: [PATCH v4 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Alistair Francis
,
00:23
Re: [PATCH] target/riscv: correct "code should not be reached" for x-rv128
,
Alistair Francis
,
00:19
January 27, 2022
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
22:56
Re: [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
22:50
Re: [PATCH v2] target/riscv: correct "code should not be reached" for x-rv128
,
Alistair Francis
,
20:55
Re: [PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Alistair Francis
,
20:54
Re: [PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Alistair Francis
,
20:51
January 26, 2022
[RFC PATCH] hw/intc: Make RISC-V ACLINT mtime MMIO register writable
,
frank . chang
,
04:54
Re: [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault
,
Weiwei Li
,
04:50
Re: [RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
Weiwei Li
,
03:37
Re: [PATCH v2] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Weiwei Li
,
03:11
January 25, 2022
Re: [PATCH v2] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Richard Henderson
,
20:17
Re: [PATCH 0/2] RISC-V: Correctly generate store/amo faults
,
Richard Henderson
,
19:09
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Richard Henderson
,
16:43
Re: [PATCH v2 1/2] target/riscv: iterate over a table of decoders
,
Richard Henderson
,
16:29
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
04:45
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
04:01
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
03:54
Re: [PATCH v6 0/5] support subsets of virtual memory extension
,
Guo Ren
,
03:42
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
03:40
Re: [PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
03:13
[PATCH v6 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
01:48
[PATCH v6 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
01:48
[PATCH v6 4/5] target/riscv: add support for svinval extension
,
Weiwei Li
,
01:48
[PATCH v6 0/5] support subsets of virtual memory extension
,
Weiwei Li
,
01:47
[PATCH v6 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
01:47
[PATCH v6 3/5] target/riscv: add support for svnapot extension
,
Weiwei Li
,
01:47
Re: [PATCH v2] target/riscv: correct "code should not be reached" for x-rv128
,
LIU Zhiwei
,
00:36
January 24, 2022
Re: [PATCH v2] target/riscv: correct "code should not be reached" for x-rv128
,
Philippe Mathieu-Daudé
,
18:08
Re: [PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Alistair Francis
,
16:35
[PATCH v2] target/riscv: correct "code should not be reached" for x-rv128
,
Frédéric Pétrot
,
15:25
[PATCH v2] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Muellner
,
09:00
Re: [RFC 5/5] target/riscv: Enable privileged spec version 1.12
,
Christoph Müllner
,
08:32
Re: [PATCH] target/riscv: correct "code should not be reached" for x-rv128
,
Frédéric Pétrot
,
06:05
Re: [PATCH] target/riscv: correct "code should not be reached" for x-rv128
,
LIU Zhiwei
,
03:48
Re: [RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
,
Richard Henderson
,
02:59
Re: [RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops.
,
Richard Henderson
,
02:56
[PATCH] target/riscv: correct "code should not be reached" for x-rv128
,
Frédéric Pétrot
,
02:50
Re: [PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault
,
LIU Zhiwei
,
00:38
Re: [PATCH 0/2] RISC-V: Correctly generate store/amo faults
,
LIU Zhiwei
,
00:18
January 23, 2022
[PATCH 0/2] RISC-V: Correctly generate store/amo faults
,
Alistair Francis
,
20:02
[PATCH 1/2] accel: tcg: Allow forcing a store fault on read ops
,
Alistair Francis
,
20:01
[PATCH 2/2] targett/riscv: rva: Correctly generate a store/amo fault
,
Alistair Francis
,
20:01
Re: [PATCH v1] include: hw: remove ibex_plic.h
,
Alistair Francis
,
18:28
January 21, 2022
Re: [RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Atish Patra
,
22:31
Re: [PATCH v1] include: hw: remove ibex_plic.h
,
Philippe Mathieu-Daudé
,
05:26
Re: [RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Müllner
,
04:55
Re: [RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
03:15
Re: [PATCH v8 00/23] QEMU RISC-V AIA support
,
Alistair Francis
,
01:16
Re: [PATCH v1] include: hw: remove ibex_plic.h
,
Alistair Francis
,
01:15
[PATCH v1] include: hw: remove ibex_plic.h
,
Alistair Francis
,
00:50
January 20, 2022
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Alistair Francis
,
22:03
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
21:09
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
20:51
Re: [RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties
,
Alistair Francis
,
19:36
Re: [RFC PATCH v5 03/14] target/riscv: rvk: add support for zbkc extension
,
Alistair Francis
,
19:12
Re: [RFC PATCH v5 02/14] target/riscv: rvk: add support for zbkb extension
,
Alistair Francis
,
19:09
Re: [PATCH v8 00/23] Support UXL filed in xstatus
,
Alistair Francis
,
19:04
Re: [PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Alistair Francis
,
18:59
Re: [PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Alistair Francis
,
18:56
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
17:32
Re: [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor
,
Alistair Francis
,
16:25
Re: [PATCH v3 0/3] Improve RISC-V spike machine bios support
,
Alistair Francis
,
16:23
[RFC 5/5] target/riscv: Enable privileged spec version 1.12
,
Atish Patra
,
15:08
[RFC 4/5] target/riscv: Add *envcfg* CSRs support
,
Atish Patra
,
15:08
[RFC 2/5] target/riscv: Introduce privilege version field in the CSR ops.
,
Atish Patra
,
15:08
[RFC 3/5] target/riscv: Add support for mconfigptr
,
Atish Patra
,
15:08
[RFC 0/5] Privilege version update
,
Atish Patra
,
15:08
[RFC 1/5] target/riscv: Add the privileged spec version 1.12.0
,
Atish Patra
,
15:08
Re: [PATCH v2 1/2] target/riscv: iterate over a table of decoders
,
Philipp Tomsich
,
15:07
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
10:38
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
10:25
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
08:48
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
08:25
[PATCH v8 23/23] target/riscv: Relax UXL field for debugging
,
LIU Zhiwei
,
07:34
[PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor
,
LIU Zhiwei
,
07:34
[PATCH v8 22/23] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
07:34
[PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN
,
LIU Zhiwei
,
07:32
[PATCH v8 19/23] target/riscv: Adjust vector address with mask
,
LIU Zhiwei
,
07:31
[PATCH v8 18/23] target/riscv: Fix check range for first fault only
,
LIU Zhiwei
,
07:31
[PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE
,
LIU Zhiwei
,
07:31
[PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN
,
LIU Zhiwei
,
07:30
[PATCH v8 15/23] target/riscv: Split out the vill from vtype
,
LIU Zhiwei
,
07:29
[PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base
,
LIU Zhiwei
,
07:29
[PATCH v8 13/23] target/riscv: Calculate address according to XLEN
,
LIU Zhiwei
,
07:28
[PATCH v8 11/23] target/riscv: Create current pm fields in env
,
LIU Zhiwei
,
07:28
[PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base]
,
LIU Zhiwei
,
07:28
[PATCH v8 10/23] target/riscv: Adjust csr write mask with XLEN
,
LIU Zhiwei
,
07:27
[PATCH v8 09/23] target/riscv: Relax debug check for pm write
,
LIU Zhiwei
,
07:27
[PATCH v8 08/23] target/riscv: Use gdb xml according to max mxlen
,
LIU Zhiwei
,
07:26
[PATCH v8 07/23] target/riscv: Extend pc for runtime pc write
,
LIU Zhiwei
,
07:25
[PATCH v8 06/23] target/riscv: Ignore the pc bits above XLEN
,
LIU Zhiwei
,
07:25
[PATCH v8 05/23] target/riscv: Create xl field in env
,
LIU Zhiwei
,
07:24
[PATCH v8 04/23] target/riscv: Sign extend pc for different XLEN
,
LIU Zhiwei
,
07:24
[PATCH v8 03/23] target/riscv: Sign extend link reg for jal and jalr
,
LIU Zhiwei
,
07:23
[PATCH v8 02/23] target/riscv: Don't save pc when exception return
,
LIU Zhiwei
,
07:23
[PATCH v8 01/23] target/riscv: Adjust pmpcfg access with mxl
,
LIU Zhiwei
,
07:22
[PATCH v8 00/23] Support UXL filed in xstatus
,
LIU Zhiwei
,
07:22
Re: [PATCH v8 00/23] QEMU RISC-V AIA support
,
Anup Patel
,
07:11
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
07:06
[PATCH v3 3/3] roms/opensbi: Remove ELF images
,
Anup Patel
,
06:58
[PATCH v3 2/3] hw/riscv: Remove macros for ELF BIOS image names
,
Anup Patel
,
06:57
[PATCH v3 1/3] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
06:57
[PATCH v3 0/3] Improve RISC-V spike machine bios support
,
Anup Patel
,
06:57
Re: [RESEND] target/riscv: fix RV128 lq encoding
,
Christoph Müllner
,
05:58
Re: [PATCH v2 3/3] roms/opensbi: Remove ELF images
,
Anup Patel
,
05:39
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
03:19
Re: [PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
02:53
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
00:15
January 19, 2022
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
Alistair Francis
,
22:30
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
21:33
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
21:12
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
,
Alistair Francis
,
19:36
Re: [RESEND] target/riscv: fix RV128 lq encoding
,
Philipp Tomsich
,
15:04
Re: [RESEND] target/riscv: fix RV128 lq encoding
,
Frédéric Pétrot
,
14:45
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
11:22
Re: [PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
10:38
[PATCH v8 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Anup Patel
,
10:28
[PATCH v8 22/23] docs/system: riscv: Document AIA options for virt machine
,
Anup Patel
,
10:28
[PATCH v8 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Anup Patel
,
10:28
[PATCH v8 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
10:28
[PATCH v8 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Anup Patel
,
10:28
[PATCH v8 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
10:28
[PATCH v8 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
,
Anup Patel
,
10:28
[PATCH v8 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Anup Patel
,
10:28
[PATCH v8 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
10:27
[PATCH v8 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
10:27
[PATCH v8 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
10:27
[PATCH v8 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Anup Patel
,
10:27
[PATCH v8 12/23] target/riscv: Implement AIA interrupt filtering CSRs
,
Anup Patel
,
10:27
[PATCH v8 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Anup Patel
,
10:27
[PATCH v8 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
10:27
[PATCH v8 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Anup Patel
,
10:27
[PATCH v8 07/23] target/riscv: Add defines for AIA CSRs
,
Anup Patel
,
10:27
[PATCH v8 06/23] target/riscv: Add AIA cpu feature
,
Anup Patel
,
10:26
[PATCH v8 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
,
Anup Patel
,
10:26
[PATCH v8 04/23] target/riscv: Improve delivery of guest external interrupts
,
Anup Patel
,
10:26
[PATCH v8 03/23] target/riscv: Implement hgeie and hgeip CSRs
,
Anup Patel
,
10:26
[PATCH v8 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Anup Patel
,
10:26
[PATCH v8 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Anup Patel
,
10:26
[PATCH v8 00/23] QEMU RISC-V AIA support
,
Anup Patel
,
10:26
[RFC PATCH v5 12/14] target/riscv: rvk: add CSR support for Zkr
,
Weiwei Li
,
06:39
[RFC PATCH v5 14/14] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
06:39
[RFC PATCH v5 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
,
Weiwei Li
,
06:39
[RFC PATCH v5 11/14] target/riscv: rvk: add support for zksed/zksh extension
,
Weiwei Li
,
06:39
[RFC PATCH v5 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
,
Weiwei Li
,
06:38
[RFC PATCH v5 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
,
Weiwei Li
,
06:38
[RFC PATCH v5 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
,
Weiwei Li
,
06:38
[RFC PATCH v5 05/14] crypto: move sm4_sbox from target/arm
,
Weiwei Li
,
06:38
[RFC PATCH v5 04/14] target/riscv: rvk: add support for zbkx extension
,
Weiwei Li
,
06:38
[RFC PATCH v5 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
,
Weiwei Li
,
06:38
[RFC PATCH v5 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*
,
Weiwei Li
,
06:38
[RFC PATCH v5 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
,
Weiwei Li
,
06:38
[RFC PATCH v5 02/14] target/riscv: rvk: add support for zbkb extension
,
Weiwei Li
,
06:38
[RFC PATCH v5 00/14] support subsets of scalar crypto extension
,
Weiwei Li
,
06:38
[RFC PATCH v5 03/14] target/riscv: rvk: add support for zbkc extension
,
Weiwei Li
,
06:38
Re: [PATCH v2 1/2] target/riscv: iterate over a table of decoders
,
Philippe Mathieu-Daudé
,
06:31
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philippe Mathieu-Daudé
,
06:18
Re: [PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names
,
Bin Meng
,
01:56
Re: [PATCH v2 1/3] hw/riscv: spike: Allow using binary firmware as bios
,
Bin Meng
,
01:56
Re: [PATCH v2 3/3] roms/opensbi: Remove ELF images
,
Bin Meng
,
01:56
[PATCH v7 22/22] target/riscv: Relax UXL field for debugging
,
LIU Zhiwei
,
00:29
[PATCH v7 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
00:29
[PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN
,
LIU Zhiwei
,
00:28
[PATCH v7 19/22] target/riscv: Adjust vector address with mask
,
LIU Zhiwei
,
00:28
[PATCH v7 18/22] target/riscv: Fix check range for first fault only
,
LIU Zhiwei
,
00:27
[PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE
,
LIU Zhiwei
,
00:27
[PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN
,
LIU Zhiwei
,
00:26
[PATCH v7 15/22] target/riscv: Split out the vill from vtype
,
LIU Zhiwei
,
00:26
[PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base
,
LIU Zhiwei
,
00:26
[PATCH v7 13/22] target/riscv: Calculate address according to XLEN
,
LIU Zhiwei
,
00:26
[PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base]
,
LIU Zhiwei
,
00:24
[PATCH v7 11/22] target/riscv: Create current pm fields in env
,
LIU Zhiwei
,
00:24
[PATCH v7 10/22] target/riscv: Adjust csr write mask with XLEN
,
LIU Zhiwei
,
00:23
[PATCH v7 09/22] target/riscv: Relax debug check for pm write
,
LIU Zhiwei
,
00:23
[PATCH v7 08/22] target/riscv: Use gdb xml according to max mxlen
,
LIU Zhiwei
,
00:23
[PATCH v7 07/22] target/riscv: Extend pc for runtime pc write
,
LIU Zhiwei
,
00:22
[PATCH v7 06/22] target/riscv: Ignore the pc bits above XLEN
,
LIU Zhiwei
,
00:21
[PATCH v7 05/22] target/riscv: Create xl field in env
,
LIU Zhiwei
,
00:21
[PATCH v7 04/22] target/riscv: Sign extend pc for different XLEN
,
LIU Zhiwei
,
00:20
[PATCH v7 03/22] target/riscv: Sign extend link reg for jal and jalr
,
LIU Zhiwei
,
00:20
[PATCH v7 02/22] target/riscv: Don't save pc when exception return
,
LIU Zhiwei
,
00:19
[PATCH v7 01/22] target/riscv: Adjust pmpcfg access with mxl
,
LIU Zhiwei
,
00:19
[PATCH v7 00/22] Support UXL filed in xstatus
,
LIU Zhiwei
,
00:18
January 18, 2022
Re: [PATCH v6 05/22] target/riscv: Create xl field in env
,
Alistair Francis
,
22:44
Re: [PATCH v6 05/22] target/riscv: Create xl field in env
,
LIU Zhiwei
,
22:37
Re: [PATCH v6 22/22] target/riscv: Relax UXL field for debugging
,
Alistair Francis
,
22:35
Re: [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN
,
Alistair Francis
,
22:31
Re: [PATCH v6 05/22] target/riscv: Create xl field in env
,
Alistair Francis
,
22:24
Re: [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr
,
Alistair Francis
,
22:21
Re: [PATCH v6 01/22] target/riscv: Adjust pmpcfg access with mxl
,
Alistair Francis
,
22:20
Re: [RESEND PATCH v3 1/7] target/riscv: Add initial support for native debug
,
Alistair Francis
,
22:16
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
LIU Zhiwei
,
22:14
Re: [RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write
,
Alistair Francis
,
22:06
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Alistair Francis
,
20:31
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Alistair Francis
,
20:20
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
18:22
Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Alistair Francis
,
17:54
Re: [PATCH v2 3/3] roms/opensbi: Remove ELF images
,
Alistair Francis
,
17:33
Re: [PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names
,
Alistair Francis
,
17:31
Re: [PATCH v2 1/3] hw/riscv: spike: Allow using binary firmware as bios
,
Alistair Francis
,
17:30
Re: [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
,
Alistair Francis
,
17:26
Re: [RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Atish Patra
,
15:31
[RESEND] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Muellner
,
11:33
[RESEND] target/riscv: fix RV128 lq encoding
,
Christoph Muellner
,
11:32
[PATCH] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Muellner
,
11:23
Re: [PATCH] target/riscv: fix RV128 lq encoding
,
Christoph Müllner
,
11:23
Re: [PATCH] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions
,
Christoph Müllner
,
11:22
[PATCH] target/riscv: fix RV128 lq encoding
,
Christoph Muellner
,
11:22
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
06:57
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
06:55
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
06:29
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Anup Patel
,
06:29
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Anup Patel
,
06:27
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
06:21
[PATCH v2 3/3] roms/opensbi: Remove ELF images
,
Anup Patel
,
06:18
[PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names
,
Anup Patel
,
06:18
[PATCH v2 1/3] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
06:18
[PATCH v2 0/3] Improve RISC-V spike machine bios support
,
Anup Patel
,
06:18
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
06:15
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Anup Patel
,
06:04
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
04:10
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Anup Patel
,
03:51
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
03:34
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
03:33
Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension
,
Weiwei Li
,
03:32
Re: [PATCH v4 0/7] support subsets of scalar crypto extension
,
Weiwei Li
,
03:24
Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
,
Weiwei Li
,
03:22
Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
,
Weiwei Li
,
03:14
Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
03:10
Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
,
Weiwei Li
,
03:09
Re: [PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
02:43
Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
02:39
Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Alistair Francis
,
00:54
Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
00:27
Re: [PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Alistair Francis
,
00:20
January 17, 2022
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Alistair Francis
,
23:52
Re: [PATCH] target/riscv: Ignore reserved bits in PTE for RV64
,
Alistair Francis
,
23:51
Re: [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
,
Alistair Francis
,
23:43
Re: [PATCH v4 0/7] support subsets of scalar crypto extension
,
Alistair Francis
,
23:42
Re: [PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
,
Alistair Francis
,
23:40
Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
,
Alistair Francis
,
23:36
Re: [PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Alistair Francis
,
23:24
Re: [PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
,
Alistair Francis
,
23:22
Re: [PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Frank Chang
,
23:10
Re: [PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Frank Chang
,
23:03
Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
22:51
Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
22:41
Re: [PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Anup Patel
,
22:35
Re: [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
22:34
Re: [PATCH v5 3/5] target/riscv: add support for svnapot extension
,
Anup Patel
,
22:32
Re: [PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Anup Patel
,
22:31
[PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
,
frank . chang
,
20:47
[PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
,
frank . chang
,
20:47
[PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
,
frank . chang
,
20:47
[PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
,
frank . chang
,
20:47
[PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
,
frank . chang
,
20:46
[PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns
,
frank . chang
,
20:46
[PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
,
frank . chang
,
20:46
[PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
,
frank . chang
,
20:46
[PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
,
frank . chang
,
20:46
[PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
,
frank . chang
,
20:46
[PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
,
frank . chang
,
20:46
[PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
,
frank . chang
,
20:46
[PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
,
frank . chang
,
20:46
[PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
,
frank . chang
,
20:46
[PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
,
frank . chang
,
20:45
[PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
,
frank . chang
,
20:45
[PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns
,
frank . chang
,
20:45
[PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
,
frank . chang
,
20:45
Re: [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
,
Frank Chang
,
20:37
[PATCH v5 4/5] target/riscv: add support for svinval extension
,
Weiwei Li
,
20:17
[PATCH v5 5/5] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
20:17
[PATCH v5 2/5] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
20:17
[PATCH v5 3/5] target/riscv: add support for svnapot extension
,
Weiwei Li
,
20:17
[PATCH v5 0/5] support subsets of virtual memory extension
,
Weiwei Li
,
20:17
[PATCH v5 1/5] target/riscv: Ignore reserved bits in PTE for RV64
,
Weiwei Li
,
20:17
Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
,
Weiwei Li
,
20:10
Re: [PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
,
Alistair Francis
,
18:29
Re: [PATCH 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
,
Alistair Francis
,
17:57
Re: [PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
,
Alistair Francis
,
17:57
Re: [PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
,
Alistair Francis
,
17:57
Re: [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
,
Alistair Francis
,
17:56
Re: [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
,
Alistair Francis
,
17:56
Re: [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns
,
Alistair Francis
,
17:55
Re: [PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
,
Alistair Francis
,
17:54
Re: [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
,
Alistair Francis
,
17:54
Re: [PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
,
Alistair Francis
,
17:53
Re: [PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
,
Alistair Francis
,
17:51
Re: [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
,
Alistair Francis
,
17:50
Re: [PATCH v5 00/13] Add riscv kvm accel support
,
Alistair Francis
,
17:48
Re: [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
,
Alistair Francis
,
17:39
Re: [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
,
Alistair Francis
,
17:32
Re: [PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
,
Alistair Francis
,
17:30
Re: [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
,
Alistair Francis
,
17:27
Re: [PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
,
Alistair Francis
,
17:23
Re: [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns
,
Alistair Francis
,
17:22
[PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Anup Patel
,
08:37
[PATCH v7 06/23] target/riscv: Add AIA cpu feature
,
Anup Patel
,
08:37
[PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
08:33
[PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Anup Patel
,
08:33
[PATCH v7 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine
,
Anup Patel
,
08:33
[PATCH v7 22/23] docs/system: riscv: Document AIA options for virt machine
,
Anup Patel
,
08:33
[PATCH v7 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
08:33
[PATCH v7 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
,
Anup Patel
,
08:33
[PATCH v7 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine
,
Anup Patel
,
08:33
[PATCH v7 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
,
Anup Patel
,
08:33
[PATCH v7 07/23] target/riscv: Add defines for AIA CSRs
,
Anup Patel
,
08:33
[PATCH v7 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Anup Patel
,
08:32
[PATCH v7 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Anup Patel
,
08:32
[PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
08:32
[PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
08:32
[PATCH v7 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Anup Patel
,
08:31
[PATCH v7 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
08:31
[PATCH v7 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
08:31
[PATCH v7 12/23] target/riscv: Implement AIA interrupt filtering CSRs
,
Anup Patel
,
08:31
[PATCH v7 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Anup Patel
,
08:30
[PATCH v7 04/23] target/riscv: Improve delivery of guest external interrupts
,
Anup Patel
,
08:30
[PATCH v7 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Anup Patel
,
08:30
[PATCH v7 00/23] QEMU RISC-V AIA support
,
Anup Patel
,
08:30
[PATCH v7 03/23] target/riscv: Implement hgeie and hgeip CSRs
,
Anup Patel
,
08:30
Re: [PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions
,
Frank Chang
,
07:56
Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
03:29
Re: [PATCH v4 4/4] target/riscv: add support for svpbmt extension
,
Guo Ren
,
02:19
[PATCH] target/riscv: Ignore reserved bits in PTE for RV64
,
guoren
,
02:15
January 15, 2022
Re: [PATCH v4 2/4] target/riscv: add support for svnapot extension
,
Anup Patel
,
23:30
[PATCH v4 1/4] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
,
Weiwei Li
,
22:01
[PATCH v4 0/4] support subsets of virtual memory extension
,
Weiwei Li
,
22:01
[PATCH v4 2/4] target/riscv: add support for svnapot extension
,
Weiwei Li
,
22:01
[PATCH v4 3/4] target/riscv: add support for svinval extension
,
Weiwei Li
,
22:01
[PATCH v4 4/4] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
22:01
January 14, 2022
[PATCH] hw/riscv: spike: Allow using binary firmware as bios
,
Anup Patel
,
11:05
Re: [PATCH v3 3/3] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
09:37
Re: [PATCH v3 2/3] target/riscv: add support for svinval extension
,
Weiwei Li
,
09:36
Re: [PATCH v3 2/3] target/riscv: add support for svinval extension
,
Anup Patel
,
09:02
Re: [PATCH v3 3/3] target/riscv: add support for svpbmt extension
,
Anup Patel
,
08:59
Re: [PATCH v3 2/3] target/riscv: add support for svinval extension
,
Weiwei Li
,
08:54
Re: [PATCH v3 2/3] target/riscv: add support for svinval extension
,
Anup Patel
,
08:40
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
07:59
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
07:04
Re: [PATCH v6 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
,
Frank Chang
,
04:49
Re: [PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs
,
Frank Chang
,
01:37
January 13, 2022
[PATCH v3 2/3] target/riscv: add support for svinval extension
,
Weiwei Li
,
20:41
[PATCH v3 3/3] target/riscv: add support for svpbmt extension
,
Weiwei Li
,
20:41
[PATCH v3 0/3] support subsets of virtual memory extension
,
Weiwei Li
,
20:41
[PATCH v3 1/3] target/riscv: add support for svnapot extension
,
Weiwei Li
,
20:41
[PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
15:21
[PATCH v2 1/2] target/riscv: iterate over a table of decoders
,
Philipp Tomsich
,
15:21
Re: [PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs
,
Frank Chang
,
09:35
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
09:21
Re: [PATCH v6 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Anup Patel
,
07:22
[PATCH v6 22/22] target/riscv: Relax UXL field for debugging
,
LIU Zhiwei
,
06:51
[PATCH v6 21/22] target/riscv: Enable uxl field write
,
LIU Zhiwei
,
06:50
[PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN
,
LIU Zhiwei
,
06:50
[PATCH v6 19/22] target/riscv: Adjust vector address with mask
,
LIU Zhiwei
,
06:50
[PATCH v6 18/22] target/riscv: Fix check range for first fault only
,
LIU Zhiwei
,
06:49
[PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE
,
LIU Zhiwei
,
06:48
[PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN
,
LIU Zhiwei
,
06:48
[PATCH v6 15/22] target/riscv: Split out the vill from vtype
,
LIU Zhiwei
,
06:47
[PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base
,
LIU Zhiwei
,
06:47
[PATCH v6 13/22] target/riscv: Calculate address according to XLEN
,
LIU Zhiwei
,
06:47
[PATCH v6 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base]
,
LIU Zhiwei
,
06:46
[PATCH v6 11/22] target/riscv: Create current pm fields in env
,
LIU Zhiwei
,
06:45
[PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN
,
LIU Zhiwei
,
06:45
[PATCH v6 09/22] target/riscv: Relax debug check for pm write
,
LIU Zhiwei
,
06:44
[PATCH v6 08/22] target/riscv: Use gdb xml according to max mxlen
,
LIU Zhiwei
,
06:44
[PATCH v6 07/22] target/riscv: Extend pc for runtime pc write
,
LIU Zhiwei
,
06:43
[PATCH v6 06/22] target/riscv: Ignore the pc bits above XLEN
,
LIU Zhiwei
,
06:43
[PATCH v6 05/22] target/riscv: Create xl field in env
,
LIU Zhiwei
,
06:42
[PATCH v6 04/22] target/riscv: Sign extend pc for different XLEN
,
LIU Zhiwei
,
06:42
[PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr
,
LIU Zhiwei
,
06:42
[PATCH v6 02/22] target/riscv: Don't save pc when exception return
,
LIU Zhiwei
,
06:42
[PATCH v6 01/22] target/riscv: Adjust pmpcfg access with mxl
,
LIU Zhiwei
,
06:40
[PATCH v6 00/22] Support UXL filed in xstatus
,
LIU Zhiwei
,
06:40
Re: [PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Anup Patel
,
05:49
Re: [PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Anup Patel
,
05:48
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
05:46
Re: [PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts
,
Frank Chang
,
02:51
Re: [PATCH v6 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation
,
Frank Chang
,
02:26
January 12, 2022
Re: [PATCH v5 13/13] target/riscv: enable riscv kvm accel
,
Anup Patel
,
23:42
Re: [PATCH v5 06/13] target/riscv: Support start kernel directly by KVM
,
Anup Patel
,
23:35
Re: [PATCH v5 13/13] target/riscv: enable riscv kvm accel
,
Alistair Francis
,
23:31
[PATCH v4 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
20:51
[PATCH v4 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Weiwei Li
,
20:51
[PATCH v4 0/6] support subsets of Float-Point in Integer Registers extensions
,
Weiwei Li
,
20:51
[PATCH v4 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Weiwei Li
,
20:51
[PATCH v4 5/6] target/riscv: add support for zhinx/zhinxmin
,
Weiwei Li
,
20:51
[PATCH v4 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
20:51
[PATCH v4 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
20:51
Re: [PATCH v6 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
,
Frank Chang
,
11:47
Re: [PATCH v6 14/23] target/riscv: Implement AIA xiselect and xireg CSRs
,
Frank Chang
,
11:40
Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation
,
Bin Meng
,
09:02
Re: [PATCH v6 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Frank Chang
,
08:26
Re: [PATCH v6 22/23] docs/system: riscv: Document AIA options for virt machine
,
Frank Chang
,
08:23
Re: [PATCH v6 17/23] target/riscv: Allow users to force enable AIA CSRs in HART
,
Frank Chang
,
08:20
Re: [PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs
,
Frank Chang
,
08:15
Re: [PATCH v6 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback
,
Frank Chang
,
08:00
Re: [PATCH v6 07/23] target/riscv: Add defines for AIA CSRs
,
Frank Chang
,
07:57
Re: [PATCH v6 06/23] target/riscv: Add AIA cpu feature
,
Frank Chang
,
07:34
Re: [PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation
,
Frank Chang
,
07:34
Re: [PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
,
Frank Chang
,
07:30
Re: [PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
,
Frank Chang
,
07:16
[PATCH v5 13/13] target/riscv: enable riscv kvm accel
,
Yifei Jiang
,
03:14
[PATCH v5 12/13] target/riscv: Support virtual time context synchronization
,
Yifei Jiang
,
03:14
[PATCH v5 11/13] target/riscv: Implement virtual time adjusting with vm state changing
,
Yifei Jiang
,
03:14
[PATCH v5 10/13] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Yifei Jiang
,
03:14
[PATCH v5 09/13] target/riscv: Add host cpu type
,
Yifei Jiang
,
03:14
[PATCH v5 08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Yifei Jiang
,
03:13
[PATCH v5 07/13] target/riscv: Support setting external interrupt by KVM
,
Yifei Jiang
,
03:13
[PATCH v5 06/13] target/riscv: Support start kernel directly by KVM
,
Yifei Jiang
,
03:13
[PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers
,
Yifei Jiang
,
03:13
[PATCH v5 04/13] target/riscv: Implement kvm_arch_get_registers
,
Yifei Jiang
,
03:13
[PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu
,
Yifei Jiang
,
03:13
[PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Yifei Jiang
,
03:13
[PATCH v5 01/13] update-linux-headers: Add asm-riscv/kvm.h
,
Yifei Jiang
,
03:13
[PATCH v5 00/13] Add riscv kvm accel support
,
Yifei Jiang
,
03:13
RE: [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM
,
Jiangyifei
,
03:08
RE: [PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Jiangyifei
,
03:04
RE: [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers
,
Jiangyifei
,
03:01
January 11, 2022
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
22:01
Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
14:58
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Anup Patel
,
12:18
[PATCH v2 2/2] hw: timer: ibex_timer: update/add reg address
,
Alistair Francis
,
02:11
[PATCH v2 1/2] riscv: opentitan: fixup plic stride len
,
Alistair Francis
,
02:11
Re: [PATCH v6 12/23] target/riscv: Implement AIA interrupt filtering CSRs
,
Frank Chang
,
01:01
January 10, 2022
[PATCH v4 4/7] target/riscv: rvk: add implementation of instructions for Zk*
,
Weiwei Li
,
22:52
[PATCH v4 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
,
Weiwei Li
,
22:52
[PATCH v4 2/7] target/riscv: rvk: add implementation of instructions for Zbk*
,
Weiwei Li
,
22:52
[PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr
,
Weiwei Li
,
22:52
[PATCH v4 0/7] support subsets of scalar crypto extension
,
Weiwei Li
,
22:52
[PATCH v4 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto
,
Weiwei Li
,
22:52
[PATCH v4 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*
,
Weiwei Li
,
22:52
[PATCH v4 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
22:52
Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
,
Wilfred Mallawa
,
20:32
Re: [PATCH v4 06/12] target/riscv: Support start kernel directly by KVM
,
Alistair Francis
,
19:28
Re: [PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Alistair Francis
,
18:10
Re: [PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers
,
Alistair Francis
,
18:07
Re: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Kumar Patra
,
17:43
Re: [PATCH v4 08/11] target/riscv: Add sscofpmf extension support
,
Atish Kumar Patra
,
17:38
Re: [PATCH v4 09/11] target/riscv: Simplify counter predicate function
,
Atish Kumar Patra
,
17:35
Re: [PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Alistair Francis
,
17:33
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
08:26
Re: [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities
,
Frank Chang
,
08:08
Re: [PATCH v4 08/11] target/riscv: Add sscofpmf extension support
,
Anup Patel
,
06:34
Re: [PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Philippe Mathieu-Daudé
,
04:16
Re: [PATCH v4 09/11] target/riscv: Simplify counter predicate function
,
Bin Meng
,
03:27
Re: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Bin Meng
,
02:55
Re: [PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Weiwei Li
,
02:45
Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address
,
Bin Meng
,
02:40
Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
,
Bin Meng
,
02:34
Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation
,
Bin Meng
,
02:26
Re: [PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties
,
Alistair Francis
,
02:07
Re: [PATCH v4 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Alistair Francis
,
01:53
Re: [PATCH v4 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Alistair Francis
,
01:49
Re: [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable
,
Alistair Francis
,
01:47
Re: [PATCH 2/2] hw: timer: ibex_timer: update/add reg address
,
Alistair Francis
,
01:17
Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
,
Alistair Francis
,
01:16
Re: [PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Alistair Francis
,
01:15
[PATCH 2/2] hw: timer: ibex_timer: update/add reg address
,
Alistair Francis
,
01:13
[PATCH 1/2] riscv: opentitan: fixup plic stride len
,
Alistair Francis
,
01:13
Re: [PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Bin Meng
,
00:58
[PATCH] hw: timer: ibex_timer: Fixup reading w/o register
,
Alistair Francis
,
00:16
January 09, 2022
[PATCH v4 05/12] target/riscv: Implement kvm_arch_put_registers
,
Yifei Jiang
,
20:39
[PATCH v4 09/12] target/riscv: Add host cpu type
,
Yifei Jiang
,
20:39
[PATCH v4 11/12] target/riscv: Implement virtual time adjusting with vm state changing
,
Yifei Jiang
,
20:39
[PATCH v4 12/12] target/riscv: Support virtual time context synchronization
,
Yifei Jiang
,
20:39
[PATCH v4 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer
,
Yifei Jiang
,
20:39
[PATCH v4 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Yifei Jiang
,
20:39
[PATCH v4 04/12] target/riscv: Implement kvm_arch_get_registers
,
Yifei Jiang
,
20:39
[PATCH v4 07/12] target/riscv: Support setting external interrupt by KVM
,
Yifei Jiang
,
20:39
[PATCH v4 06/12] target/riscv: Support start kernel directly by KVM
,
Yifei Jiang
,
20:39
[PATCH v4 03/12] target/riscv: Implement function kvm_arch_init_vcpu
,
Yifei Jiang
,
20:39
[PATCH v4 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface
,
Yifei Jiang
,
20:39
[PATCH v4 01/12] update-linux-headers: Add asm-riscv/kvm.h
,
Yifei Jiang
,
20:39
[PATCH v4 00/12] Add riscv kvm accel support
,
Yifei Jiang
,
20:38
RE: [PATCH v3 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Jiangyifei
,
20:33
RE: [PATCH v3 06/12] target/riscv: Support start kernel directly by KVM
,
Jiangyifei
,
20:28
Re: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
20:23
Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target
,
Alistair Francis
,
17:07
[PATCH v1 2/2] target/riscv: Add XVentanaCondOps custom extension
,
Philipp Tomsich
,
15:56
January 08, 2022
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
08:28
Re: [PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Anup Patel
,
07:03
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Anup Patel
,
07:01
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
01:35
January 07, 2022
Re: [PATCH v3 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
20:17
Re: [PATCH v3 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
20:15
Re: [PATCH v3 4/6] target/riscv: add support for zdinx
,
Richard Henderson
,
15:54
Re: [PATCH v3 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Richard Henderson
,
15:48
Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Frédéric Pétrot
,
11:46
Re: [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Philippe Mathieu-Daudé
,
09:36
[PATCH v3 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Weiwei Li
,
06:28
[PATCH v3 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
06:28
[PATCH v3 5/6] target/riscv: add support for zhinx/zhinxmin
,
Weiwei Li
,
06:28
[PATCH v3 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
06:28
[PATCH v3 0/6] support subsets of Float-Point in Integer Registers extensions
,
Weiwei Li
,
06:28
[PATCH v3 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties
,
Weiwei Li
,
06:28
[PATCH v3 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
06:28
Re: [PATCH v4 06/11] target/riscv: Add support for hpmcounters/hpmevents
,
Bin Meng
,
05:52
Re: [PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation
,
Frank Chang
,
03:53
Re: [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable
,
Bin Meng
,
02:51
Re: [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode
,
Bin Meng
,
02:51
Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Alistair Francis
,
01:48
Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Frédéric Pétrot
,
01:23
January 06, 2022
Re: [PATCH v4 0/3] RISC-V: Populate mtval and stval
,
Alistair Francis
,
22:33
[PATCH v4 09/11] target/riscv: Simplify counter predicate function
,
Atish Patra
,
21:14
[PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
21:14
[PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode
,
Atish Patra
,
21:14
[PATCH v4 08/11] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
21:14
[PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function
,
Atish Patra
,
21:14
[PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
21:14
[PATCH v4 03/11] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
21:14
[PATCH v4 06/11] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
21:14
[PATCH v4 05/11] target/riscv: Implement mcountinhibit CSR
,
Atish Patra
,
21:14
[PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
21:14
[PATCH v4 10/11] target/riscv: Add few cache related PMU events
,
Atish Patra
,
21:14
[PATCH v4 00/11] Improve PMU support
,
Atish Patra
,
21:14
Re: [PATCH v4 2/3] target/riscv: Fixup setting GVA
,
Bin Meng
,
21:07
Re: [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
19:39
Re: [PATCH] target/riscv: Fix position of 'experimental' comment
,
Alistair Francis
,
17:18
Re: [PATCH] target/riscv: Fix position of 'experimental' comment
,
Alistair Francis
,
16:30
Re: [PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Alistair Francis
,
16:24
[PATCH v8 17/18] target/riscv: modification of the trans_csrxx for 128-bit support
,
Frédéric Pétrot
,
16:02
[PATCH v8 18/18] target/riscv: actual functions to realize crs 128-bit insns
,
Frédéric Pétrot
,
16:02
[PATCH v8 13/18] target/riscv: support for 128-bit arithmetic instructions
,
Frédéric Pétrot
,
16:02
[PATCH v8 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns
,
Frédéric Pétrot
,
16:02
[PATCH v8 12/18] target/riscv: support for 128-bit shift instructions
,
Frédéric Pétrot
,
16:02
[PATCH v8 11/18] target/riscv: support for 128-bit U-type instructions
,
Frédéric Pétrot
,
16:02
[PATCH v8 14/18] target/riscv: support for 128-bit M extension
,
Frédéric Pétrot
,
16:02
[PATCH v8 15/18] target/riscv: adding high part of some csrs
,
Frédéric Pétrot
,
16:02
[PATCH v8 10/18] target/riscv: support for 128-bit bitwise instructions
,
Frédéric Pétrot
,
16:01
[PATCH v8 07/18] target/riscv: setup everything for rv64 to support rv128 execution
,
Frédéric Pétrot
,
16:01
[PATCH v8 09/18] target/riscv: accessors to registers upper part and 128-bit load/store
,
Frédéric Pétrot
,
16:01
[PATCH v8 08/18] target/riscv: moving some insns close to similar insns
,
Frédéric Pétrot
,
16:01
[PATCH v8 05/18] target/riscv: separation of bitwise logic and arithmetic helpers
,
Frédéric Pétrot
,
16:01
[PATCH v8 03/18] qemu/int128: addition of div/rem 128-bit operations
,
Frédéric Pétrot
,
16:01
[PATCH v8 06/18] target/riscv: array for the 64 upper bits of 128-bit registers
,
Frédéric Pétrot
,
16:01
[PATCH v8 04/18] target/riscv: additional macros to check instruction support
,
Frédéric Pétrot
,
16:01
[PATCH v8 01/18] exec/memop: Adding signedness to quad definitions
,
Frédéric Pétrot
,
16:01
[PATCH v8 02/18] exec/memop: Adding signed quad and octo defines
,
Frédéric Pétrot
,
16:01
[PATCH v8 00/18] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
16:01
Re: [PATCH] target/riscv: Fix position of 'experimental' comment
,
Philippe Mathieu-Daudé
,
14:51
Re: [PATCH v7 00/18] Adding partial support for 128-bit riscv target
,
Frédéric Pétrot
,
10:36
[PATCH] target/riscv: Fix position of 'experimental' comment
,
Philipp Tomsich
,
10:05
Re: [PATCH] target/riscv: Fix position of 'experimental' comment
,
Bin Meng
,
09:50
Re: [PATCH v7 00/18] Adding partial support for 128-bit riscv target
,
Alistair Francis
,
03:33
Re: [PATCH v7 18/18] target/riscv: actual functions to realize crs 128-bit insns
,
Alistair Francis
,
01:48
January 05, 2022
Re: [PATCH v4 2/3] target/riscv: Fixup setting GVA
,
Alistair Francis
,
23:04
Re: [PATCH v7 17/18] target/riscv: modification of the trans_csrxx for 128-bit support
,
Alistair Francis
,
20:58
Re: [PATCH v7 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns
,
Alistair Francis
,
20:25
Re: [PATCH v7 14/18] target/riscv: support for 128-bit M extension
,
Alistair Francis
,
20:24
Re: [PATCH v7 13/18] target/riscv: support for 128-bit arithmetic instructions
,
Alistair Francis
,
20:17
Re: [PATCH v2 0/3] Fix RVV calling incorrect RFV/RVD check functions bug
,
Alistair Francis
,
17:31
Re: [PATCH v4 0/8] A collection of RISC-V cleanups and improvements
,
Alistair Francis
,
17:29
Re: [PATCH] roms/opensbi: Upgrade from v0.9 to v1.0
,
Alistair Francis
,
17:28
Re: [PATCH v3 12/12] target/riscv: Support virtual time context synchronization
,
Alistair Francis
,
17:11
[PATCH v4 8/8] hw/riscv: virt: Allow support for 32 cores
,
Alistair Francis
,
17:09
[PATCH v4 6/8] target/riscv: Enable the Hypervisor extension by default
,
Alistair Francis
,
17:09
[PATCH v4 3/8] hw/intc: sifive_plic: Cleanup the read function
,
Alistair Francis
,
17:07
[PATCH v4 7/8] hw/riscv: Use error_fatal for SoC realisation
,
Alistair Francis
,
17:07
[PATCH v4 2/8] hw/intc: sifive_plic: Cleanup the write function
,
Alistair Francis
,
17:07
[PATCH v4 1/8] hw/intc: sifive_plic: Add a reset function
,
Alistair Francis
,
17:06
Re: [PATCH v3 11/12] target/riscv: Implement virtual time adjusting with vm state changing
,
Alistair Francis
,
17:04
Re: [PATCH v3 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit
,
Alistair Francis
,
17:04
[PATCH v4 5/8] target/riscv: Mark the Hypervisor extension as non experimental
,
Alistair Francis
,
17:03
[PATCH v4 4/8] hw/intc: sifive_plic: Cleanup remaining functions
,
Alistair Francis
,
16:54
[PATCH v4 0/8] A collection of RISC-V cleanups and improvements
,
Alistair Francis
,
16:54
Re: [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
16:52
Re: [PATCH v6 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
,
Alistair Francis
,
16:50
Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
16:48
Re: [PATCH v2 3/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns
,
Alistair Francis
,
16:48
Re: [PATCH v2 2/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns
,
Alistair Francis
,
16:46
Re: [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for
,
Atish Patra
,
16:46
Re: [PATCH v2 1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns
,
Alistair Francis
,
16:44
Re: [PATCH] roms/opensbi: Upgrade from v0.9 to v1.0
,
Alistair Francis
,
16:43
January 04, 2022
Re: [PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs
,
Frank Chang
,
22:31
[RESEND PATCH v3 3/7] target/riscv: debug: Implement debug related TCGCPUOps
,
Bin Meng
,
22:09
[RESEND PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
,
Bin Meng
,
22:09
[RESEND PATCH v3 6/7] target/riscv: cpu: Enable native debug feature
,
Bin Meng
,
22:09
[RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write
,
Bin Meng
,
22:09
[RESEND PATCH v3 4/7] target/riscv: cpu: Add a config option for native debug
,
Bin Meng
,
22:09
[PATCH v3 1/7] target/riscv: Add initial support for native debug
,
Bin Meng
,
22:09
[RESEND PATCH v3 2/7] target/riscv: machine: Add debug state description
,
Bin Meng
,
22:09
[RESEND PATCH v3 1/7] target/riscv: Add initial support for native debug
,
Bin Meng
,
22:08
[RESEND PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
,
Bin Meng
,
22:08
[RESEND PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
,
Bin Meng
,
22:06
[PATCH v3 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
,
Bin Meng
,
22:02
[PATCH v3 6/7] target/riscv: cpu: Enable native debug feature
,
Bin Meng
,
22:02
[PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write
,
Bin Meng
,
22:02
[PATCH v3 3/7] target/riscv: debug: Implement debug related TCGCPUOps
,
Bin Meng
,
22:01
[PATCH v3 4/7] target/riscv: cpu: Add a config option for native debug
,
Bin Meng
,
22:01
[PATCH v3 2/7] target/riscv: machine: Add debug state description
,
Bin Meng
,
22:01
[PATCH v3 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs
,
Bin Meng
,
22:01
[PATCH v2 3/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns
,
frank . chang
,
21:23
[PATCH v2 2/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns
,
frank . chang
,
21:23
[PATCH v2 1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns
,
frank . chang
,
21:23
[PATCH v2 0/3] Fix RVV calling incorrect RFV/RVD check functions bug
,
frank . chang
,
21:23
[PATCH] roms/opensbi: Upgrade from v0.9 to v1.0
,
Bin Meng
,
20:58
Re: [PATCH v2 0/2] Align SiFive PDMA behavior to real hardware
,
Alistair Francis
,
16:55
Re: [PATCH 1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for widening fp insns
,
Alistair Francis
,
16:50
[PATCH v2 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
,
Jim Shu
,
01:35
[PATCH v2 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Jim Shu
,
01:35
[PATCH v2 0/2] Align SiFive PDMA behavior to real hardware
,
Jim Shu
,
01:34
Re: [PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Jim Shu
,
00:53
January 03, 2022
Re: [PATCH 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
,
Bin Meng
,
21:56
Re: [PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Bin Meng
,
21:55
Re: [PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
,
Alistair Francis
,
17:48
Re: [PATCH 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
,
Alistair Francis
,
17:46
Re: [PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
,
Alistair Francis
,
17:46
January 02, 2022
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
00:57
Re: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
00:54
Re: [PATCH v2 2/3] target/riscv: add support for svinval extension
,
Weiwei Li
,
00:41
January 01, 2022
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
,
Richard Henderson
,
14:49
Re: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Richard Henderson
,
14:46
Re: [PATCH v2 3/3] target/riscv: add support for svpbmt extension
,
Anup Patel
,
08:19
Re: [PATCH v2 1/3] target/riscv: add support for svnapot extension
,
Anup Patel
,
08:17
Re: [PATCH v2 2/3] target/riscv: add support for svinval extension
,
Anup Patel
,
08:15
Re: [PATCH v2 4/6] target/riscv: add support for zdinx
,
Weiwei Li
,
01:06
Re: [PATCH v2 3/6] target/riscv: add support for zfinx
,
Weiwei Li
,
01:06
Re: [PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx
,
Weiwei Li
,
00:55
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