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RE: [avr-chat] XMega PDI_DATA and PDI_CLK must be balanced?
From: |
Weddington, Eric |
Subject: |
RE: [avr-chat] XMega PDI_DATA and PDI_CLK must be balanced? |
Date: |
Tue, 31 Mar 2009 10:39:41 -0600 |
> -----Original Message-----
> From: address@hidden
> [mailto:address@hidden
> On Behalf Of Bob Paddock
> Sent: Tuesday, March 31, 2009 10:16 AM
> To: address@hidden
> Subject: [avr-chat] XMega PDI_DATA and PDI_CLK must be balanced?
>
> I'm doing a my first design with a XMega, there are sections about
> the PDI interface I'm not clear on. In AVR1005 we can read:
>
> "5.1 Hardware design requirements to make PDI work
>
> The PDI interface is a synchronous half-duplex UART
> interface. The two lines,
> PDI_DATA and PDI_CLK, must therefore be balanced. If you
> place a strong pull-up
> and decoupling cap on the PDI_CLK, which is also the Reset line, the
> clock and data
> will no longer be synchronized correctly. Therefore, during
> development you should
> remove any pull-up and decoupling capacitors. This also
> applies if using the PDI
> interface for in-system programming the XMEGA in production."
Sorry, but to be fair, I'm not a EE. My background is in software engineering.
I can't answer these types of questions for you. :-(
Your best bet would be to ask address@hidden for clarification, or your local
FAE.
Eric Weddington