|Subject:||[avr-chat] Problems with xmega DMA Controller|
|Date:||Sat, 09 Apr 2011 09:55:49 -0400|
Using an ATxmega32A4, I am trying to generate a waveform using the DAC at Port B in single-channel mode. I need to run it at 1 MHz, the maximum conversion rate. It turns out that if I set the conversion interval for 32 clocks (I'm running at 32 MHz), and then simply watch the Data Register Empty bit in the Status register and load the next sample value when I set it go high, I get exactly the output I'm looking for. So, the DAC seems happy.
Of course, I can't dedicate the firmware to watching the DAC, so I expect to get the DMA controller to take over the update. What I expected was that by selecting DACB Channel 0 as the trigger for the DMA channel, every time the Data Register Empty bit goes active, the DMA controller would perform a burst (set to one byte) and the next value would appear after the programmed conversion interval. This does not work. Nothing happens.
If, using the debugger, I manually set the Transfer Request bit in the DMA channel, then run, then stop and repeat this, I can cycle through the sample values and all the register settings make sense. So, I seem to have the DMA set up correctly. The problem seems only to be that the trigger source is not having any effect.
I have switched the Trigger Source to a Timer / Counter just to see what happens. Now I can see my sample values and they change at 1 us intervals, but the values are all jumbled up. It does not seem to matter what the Timer / Counter is doing, I get the same results. Even with the Timer / Counter running with a long period, the samples come out of the DAC every 1us, but in some bizarre order.
Does anyone have any insight into exactly how DMA triggers work? Has anyone got anything like this running? The Application Notes, of course, only deal with the simple stuff and refer you to the data sheet for "advanced features" like this.
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