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RE: [avr-gcc-list] Difficulties switching from Mega103 to Mega128

From: Scott and Roxanne Munns
Subject: RE: [avr-gcc-list] Difficulties switching from Mega103 to Mega128
Date: Tue, 12 Aug 2003 20:50:08 -0500


We've been attempting (thus far) to keep the Mega128 in Mega103
compatibility mode for purposes of this conversion.  In compatibility mode,
there are only two wait state settings (none and one).  We already have it
set to use the wait state.  Perhaps if we went to Mega128 mode, we could the
additional wait state settings to solve the problem.  But, that could open
up other gremlins in the code, too...  :(


-----Original Message-----
From: Brian Dean [mailto:address@hidden
Sent: Tuesday, August 12, 2003 8:16 PM
To: address@hidden
Cc: 'Brian Korsedal'; address@hidden
Subject: Re: [avr-gcc-list] Difficulties switching from Mega103 to

On Tue, Aug 12, 2003 at 08:04:43PM -0500, Scott and Roxanne Munns wrote:

> It appears that my colleague may have solved the problem between the
> Mega103 and the Mega128 in Mega103 compatibility mode today.  The
> timing and presentation of address and data info on the external
> memory interface has definitely changed (try comparing timing
> diagrams of both processors).  It seems that inserting a "nop" in
> between any consecutive reads and writes through the external memory
> interface "solves" the problem.  Since the code was written in
> assembly, it was easy to find and change the behavior.  As we learn
> more about the exact failure mode and whether this is an Atmel
> issue, LCD display driver issue, or just a bad combination of the
> two, I'll post updates to the list.

Maybe you've already been down this path, but the ATmega128 has a
programmable wait state delay.  See the "External Memory Control
Register A" (XMCRA) register (page 29 of the datasheet).  Perhaps that
will help?

Brian Dean, address@hidden
BDMICRO - Maker of the MAVRIC ATmega128 Dev Board

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