RE: [avr-gcc-list] Difficulties switching from Mega103 to Mega128

[Rune Christensen]

Hello

I have found the following text from the atmel mega128 datasheet

Address Latch Requirements:
---------------------------

Due to the high-speed operation of the XRAM interface, the address latch
must be
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style
74HC series
latch becomes inadequate. The External Memory Interface is designed in
compliance to
the 74AHC series latch. However, most latches can be used as long they
comply with
the main timing parameters. The main parameters for the address latch are:
• D to Q propagation delay (tPD).
• Data setup time before G low (tSU).
• Data (address) hold time after G low (TH).
The External Memory Interface is designed to guaranty minimum address hold
time
after G is asserted low of th = 5 ns. Refer to tLAXX_LD/tLLAXX_ST in
“External Data Memory
Timing” Tables 137 through Tables 144 on pages 326 - 328. The D-to-Q
propagation
delay (tPD) must be taken into consideration when calculating the access
time requirement
of the external component. The data setup time before G low (tSU) must not
exceed address valid to ALE low (tAVLLC) minus PCB wiring delay (dependent
on the
capacitive load).


Maybe the address latch could be the problem.

mega103:

one clock period between ALE low and /WR low

mega128:

1/2 clock period between ALE low  and /WR low


Best Regards
Rune Christensen


-----Original Message-----
From: address@hidden
[mailto:address@hidden Behalf Of Scott and Roxanne
Munns
Sent: Wednesday, August 13, 2003 3:50 AM
To: 'Brian Dean'
Cc: address@hidden
Subject: RE: [avr-gcc-list] Difficulties switching from Mega103 to
Mega128


Brian,

We've been attempting (thus far) to keep the Mega128 in Mega103
compatibility mode for purposes of this conversion.  In compatibility mode,
there are only two wait state settings (none and one).  We already have it
set to use the wait state.  Perhaps if we went to Mega128 mode, we could the
additional wait state settings to solve the problem.  But, that could open
up other gremlins in the code, too...  :(

Scott

-----Original Message-----
From: Brian Dean [mailto:address@hidden
Sent: Tuesday, August 12, 2003 8:16 PM
To: address@hidden
Cc: 'Brian Korsedal'; address@hidden
Subject: Re: [avr-gcc-list] Difficulties switching from Mega103 to
Mega128


On Tue, Aug 12, 2003 at 08:04:43PM -0500, Scott and Roxanne Munns wrote:

> It appears that my colleague may have solved the problem between the
> Mega103 and the Mega128 in Mega103 compatibility mode today.  The
> timing and presentation of address and data info on the external
> memory interface has definitely changed (try comparing timing
> diagrams of both processors).  It seems that inserting a "nop" in
> between any consecutive reads and writes through the external memory
> interface "solves" the problem.  Since the code was written in
> assembly, it was easy to find and change the behavior.  As we learn
> more about the exact failure mode and whether this is an Atmel
> issue, LCD display driver issue, or just a bad combination of the
> two, I'll post updates to the list.

Maybe you've already been down this path, but the ATmega128 has a
programmable wait state delay.  See the "External Memory Control
Register A" (XMCRA) register (page 29 of the datasheet).  Perhaps that
will help?

Cheers,
-Brian
--
Brian Dean, address@hidden
BDMICRO - Maker of the MAVRIC ATmega128 Dev Board
http://www.bdmicro.com/


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