|Subject:||RE: [avr-gcc-list] Difficulties switching from Mega103 to Mega128|
|Date:||Wed, 13 Aug 2003 07:04:21 -0700|
I've found the problem on our board. It seems that Port C (and maybe other ports) are setup to output by default in the 103 mode and setup to input by default in the 128 mode. I switched Port C to an output and everything worked O.K.
From: Rune Christensen [mailto:address@hidden]
Sent: Wed 8/13/2003 4:32 AM
To: address@hidden Org
Subject: RE: [avr-gcc-list] Difficulties switching from Mega103 to Mega128
I have found the following text from the atmel mega128 datasheet
Address Latch Requirements:
Due to the high-speed operation of the XRAM interface, the address latch
selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.
When operating at conditions above these frequencies, the typical old style
latch becomes inadequate. The External Memory Interface is designed in
the 74AHC series latch. However, most latches can be used as long they
the main timing parameters. The main parameters for the address latch are:
D to Q propagation delay (tPD).
Data setup time before G low (tSU).
Data (address) hold time after G low (TH).
The External Memory Interface is designed to guaranty minimum address hold
after G is asserted low of th = 5 ns. Refer to tLAXX_LD/tLLAXX_ST in
External Data Memory
Timing Tables 137 through Tables 144 on pages 326 - 328. The D-to-Q
delay (tPD) must be taken into consideration when calculating the access
of the external component. The data setup time before G low (tSU) must not
exceed address valid to ALE low (tAVLLC) minus PCB wiring delay (dependent
Maybe the address latch could be the problem.
one clock period between ALE low and /WR low
1/2 clock period between ALE low and /WR low
[mailto:address@hidden]On Behalf Of Scott and Roxanne
Sent: Wednesday, August 13, 2003 3:50 AM
To: 'Brian Dean'
Subject: RE: [avr-gcc-list] Difficulties switching from Mega103 to
We've been attempting (thus far) to keep the Mega128 in Mega103
compatibility mode for purposes of this conversion. In compatibility mode,
there are only two wait state settings (none and one). We already have it
set to use the wait state. Perhaps if we went to Mega128 mode, we could the
additional wait state settings to solve the problem. But, that could open
up other gremlins in the code, too... :(
From: Brian Dean [mailto:address@hidden]
Sent: Tuesday, August 12, 2003 8:16 PM
Cc: 'Brian Korsedal'; address@hidden
Subject: Re: [avr-gcc-list] Difficulties switching from Mega103 to
On Tue, Aug 12, 2003 at 08:04:43PM -0500, Scott and Roxanne Munns wrote:
> It appears that my colleague may have solved the problem between the
> Mega103 and the Mega128 in Mega103 compatibility mode today. The
> timing and presentation of address and data info on the external
> memory interface has definitely changed (try comparing timing
> diagrams of both processors). It seems that inserting a "nop" in
> between any consecutive reads and writes through the external memory
> interface "solves" the problem. Since the code was written in
> assembly, it was easy to find and change the behavior. As we learn
> more about the exact failure mode and whether this is an Atmel
> issue, LCD display driver issue, or just a bad combination of the
> two, I'll post updates to the list.
Maybe you've already been down this path, but the ATmega128 has a
programmable wait state delay. See the "External Memory Control
Register A" (XMCRA) register (page 29 of the datasheet). Perhaps that
Brian Dean, address@hidden
BDMICRO - Maker of the MAVRIC ATmega128 Dev Board
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