[avr-gcc-list] lock bits

[Reza Naima]

I've looked through the datasheet, as well as though some article on
avrfreaks, and I think I understand it, but want to double check.

I've enchanced my bootloader (added TEA - tiny encryption algorythm)
(will post soon if anyone is interested) so that I can distribute
encyprted binaries without fear of someone dissassembling it.  Now, I
want to make sure that no one can read the application code or
bootloader code (as it contains the TEA key) using an external device.  I
don't want the application code to be writable except through the
bootloader, and I want to make sure the bootloader is write protected as
well.  All I want to allow is the bootloader to program and read (for
verification) the application code.  That's it.

So this is what I'm thinking (for an ATmega32) :

Memory Lock Bits : LB1=0 LB2=0 -> no programing or verification allowed
Boot Lock Bit0: BLB02=1 BLBO1=1 -> No restriction for SPM or LPM 
                                   accessing the application section
Boot Lock Bit1: BLB12=0 BLB1=0 -> 
        SPM is not allowed to write to the Boot Loader section,
        and LPM executing from the Application section is not
        allowed to read from the Boot Loader section. If interrupt
        vectors are placed in the Application section, interrupts
        are disabled while executing from the Boot Loader section.


Does this sound right?  Any holes in my logic? 

Thnx,
Reza