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RE: [avr-gcc-list] Handling High Speed Interrupts

From: Larry Barello
Subject: RE: [avr-gcc-list] Handling High Speed Interrupts
Date: Wed, 22 Sep 2004 06:53:38 -0700

Forget the "naked" attribute: write your handler in assembly.  With only 74
cycles, at BEST you can only have 74 instructions... and likely a whole lot

I have done this before: 64 average cycles/interrupt and being interrupted
every 80 cycles (200khz @ 16mhz).  It still leaves an amazing amount of
power for the high level tasking stuff.  I think I was decoding four R/C
pulse channels, and generating three channels of PWM output...  I couldn't
use hardware since the H-Bridge chips had a funny signaling scheme, plus
there simply were not enough PWM channels...

-----Original Message-----
From: address@hidden
[mailto:address@hidden Behalf Of Janos Sztriko
Sent: Wednesday, September 22, 2004 6:18 AM
To: address@hidden
Subject: Re: [avr-gcc-list] Handling High Speed Interrupts


You need to use the "naked" interrupt attribute. See this links:


I hope this helps.


Ramkumar Rengaswamy wrote:

> Hi,
>    I have an application that needs to generate a Timer Output Compare
> Interrput every 10 uS. I have an ATMega128L clocked at 7.329 MHz. This
> means that I have 74 clock cycles to handle the interrupt routine and
> currently most of the clock cycles are wasted in pushing and popping
> things off the stack. Is there anyway in avr-gcc to avoid all this
> overhead and utilize all the cycles for my processing only ?
> Thanks,
> -Ram

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