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Re: [avr-gcc-list] AT90CAN128 silicon bug in conjunction w/ external RAM

From: Henrik Maier
Subject: Re: [avr-gcc-list] AT90CAN128 silicon bug in conjunction w/ external RAM
Date: Sun, 17 Apr 2005 10:02:31 +1000
User-agent: Mozilla Thunderbird 1.0 (Windows/20041206)

IN/OUT instructions in prologues/epilogues only access SPL/SPH/SREG
which should be safe in any case: doing it twice shouldn't do any harm,
setting SPL/SPH must be protected against interrupts anyway.

This is exactly why I do not fully believe Atmel's statement. Most IN/OUT instructions can be executed multiple times without harm. But anyway, as I said, I found that the bug not only relates to IN and OUT. I approached Atmel on this, see what they reply.

Just to make sure, check that you have no hardware problems with
external SRAM (try to slow down the clock frequency and see if the
problem still exists).  If your hardware is OK, then...

Done all of this, tried different hardware and much more before I even approached Atmel. If you check the links in my earlier post, you find some more background info and a little test program demonstrating the bug. End of a long journey of debugging and analysis is: Atmel _confirmed_ a bug in the chip and also that my issues relate to this bug.

Looking at Atmel's description: "... it seems that only "IN" and "OUT" instructions are concerned.", they use the term "seem" which means to me they are not quite sure.

If they are not sure, it is safest to simply say "stack in external
SRAM is broken" and stick with their recommended workaround.

I think that's what I have to live with, it doesn't make it easy from a programming point of view. It will be quite complicated to change the RTOS I am using to keep SP in internal RAM. But it's possible.


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