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[avr-gcc-list] Strangeness with UART Baud Rate

From: User Tomdean
Subject: [avr-gcc-list] Strangeness with UART Baud Rate
Date: Sun, 24 Jul 2005 19:54:07 -0700 (PDT)

I have an Atmel STK500 with ATMEGA16-16P1.  

 The UART's have several registers controlling their operation.

 UBRRH is the upper 4 bits of the divisor
 UBRRL is the lower 8 bits of the divisor

 The divisor is Fosc/(16*baud)-1.  For a 3.6864Mhz xtal, this is
 3686400/16/9600-1 or a divisor of 23.

 So, UBRRH is zero.  Set this by writing to the register with URSEL=0.
 UBRRH = (BAUD >> 8);
 UBRRL = 23;

 UDR is the UART i/o data register.

 UCSRA is the status register, also containing the U2X, the baud rate
 doubler.  Leave this zero.

 UCSRB enables the tx and rx, enable both.

 UCSRB = (1 << RXEN) | (1 << TXEN);

 UCSRC controls the frame.  Select 8 bits, no parity, two stop bits.

 UCSZ2 in UCSRB is zero.
 UCSZ<1:0> are both set, and is USBS.
 UCSRC = (1 << URSEL) | (1 << USBS) | (1 << UCSZ1) | (1 << UCSZ0);

 Looking at the XT1 pin on PORTE with a scope on a .05us/div time
 scale, gives 1/(5.4*.05e-6) or 3703703.7, close enoiugh to 3.6864 Mhz
 the clock is spec;d as.

 Using #define BAUD 3686400/16/9600-1 and playin with the FreeBSD
 serial port, gives a connection speed of 2400.
 #Using define BAUD 1000000/16/9600-1 and playin with the FreeBSD
 serial port, gives a connection speed of 9600.

 using absolute values,
 gives 9600 baud.

 So, it appears that Fosc is really 1Mhz, not 3.6764MNhz...

 Where does this come from?


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