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[avr-gcc-list] ATmega16 ADC at High Clock Rates

From: User Tomdean
Subject: [avr-gcc-list] ATmega16 ADC at High Clock Rates
Date: Tue, 16 Aug 2005 11:31:27 -0700 (PDT)

The ATmega16 datasheet states, in part,

  By default, the successive approximation circuitry requires an input
  clock frequency between 50 kHz and 200 kHz to get maximum
  resoultion.  If a lower resolution than 10 bits is needed, the input
  clock frequency to the ADC can be higher than 200 kHz to get a
  higher sample rate.

The datasheet does not specify the reduction in resolution due to a
higher clock rate.

Before I measure, does anyone know the reduction in resoultion, say,
at 1 mHz?  2 mHz?


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