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Re: [avr-gcc-list] split movhi to 2 movqi

From: Ilya Lesokhin
Subject: Re: [avr-gcc-list] split movhi to 2 movqi
Date: Fri, 20 May 2011 23:50:49 +0300

it works great, thanks for all the help.
though i have a few more questions and i'd be glad if you could answer them for me.
1. when and by whom  adjust_insn_length(...) is called?
2. to update my new pattern length all i have to do is recongenise it in adjust_insn_length(...) ?
3. to implement my new code i had to copy the functionality of out_movhi_mr_r(...) (move from register to mem).
i wanted to avoid it so at first i change it to work with my new patter (2 QI registers instead of 1 HI)
and before calling it from  output_movhi(...) i splitied the register into 2
using the following:
rtx ops[3];
ops[0] = operands[0];
unsigned int low_off = subreg_lowpart_offset (QImode, HImode);
unsigned int high_off = subreg_highpart_offset (QImode, HImode);
ops[1]= simplify_gen_subreg (QImode, operands[1], HImode, low_off);
ops[2] = simplify_gen_subreg (QImode, operands[1], HImode, high_off);
templ = out_movhi_mr_r (insn, ops, real_l);
unfourtenly it didnt work and when i tired to compile a big project it generated ldd r28, __SP_L__ which is an illigal instruction.
do you have any idea why that happend?
4. in the normal code the following appers:
if (src == const0_rtx)
operands[1] = zero_reg_rtx;
templ = out_movhi_mr_r (insn, operands, real_l);
since  zero_reg_rtx is an 8 bit register, i'm curious as to how it works?
if i do something "similar" in inline assembly
uint8_t value1 =1, value2 =2; 
(" add %0,%%B1 " "\n\t"
: "+r" (value1)"
: "r" (value2);
then the second opperand of the add is the register the is adjecent to the one that was allocated for value2, so how come the same doesnt happen with zero_reg_rtx  in out_movhi_mr_r(...)?
5. can you point me to somewhere that explains how to get the change to be accepted to the officail gcc?
thanks again,

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