[avr-gcc-list] How to reserve registers

[Omar Choudary]

Hello,

I need to combine certain assemble code with some C code in order to
optimise a counter update, since I want
to update the counter close to the CPU clock. Therefore I need this
code to be as short as possible.

I took the approach described here:
http://www.nongnu.org/avr-libc/user-manual/group__asmdemo.html

Therefore I have an interrupt declared in a .C file like this:

ISR(TIMER2_COMPA_vect)
{
    IncrementCounter();
}


and then the assembler of the IncrementCounter() is in a .S file like this:

.global IncrementCounter
IncrementCounter:
    ldi r19, 1                          ; use to increment with carry
    clc
    adc counter_b0, r19
    adc counter_b1, r1
    adc counter_b2, r1
    adc counter_b3, r1
    ret

The counter_b0 to b3 are reserved/declared like this in a .h file
which is included everywhere they are used:

#ifdef __ASSEMBLER__

// Syncronization counter, 32 bit value stored on 4 CONSECUTIVE registers
#  define counter_b0    r2
#  define counter_b1    r3
#  define counter_b2    r4
#  define counter_b3    r5

#else  /* !ASSEMBLER */

#include <stdint.h>

register uint8_t counter_b0 asm("r2");
register uint8_t counter_b1 asm("r3");
register uint8_t counter_b2 asm("r4");
register uint8_t counter_b3 asm("r5");

#endif /* ASSEMBLER */


However, to my surprise, the GCC (avr-gcc 4.5.2, OPT level = s)
happily uses the registers r2 to r5 for other purposes as well.
As a result, my counter update is messing around with functions such
as fprintf and malloc. What I get
is a scrambled LCD output (from fprintf) which before the whole timer
thing was working fine.

Any ideas how to force GCC into not using r2-r5 at all?


Basically I want to use this kind of approach and I would like to know
how to do it, rather than just
changing the approach (i.e. I want to keep very short code during the
interrupt routine).

Thanks,
  Omar