[Bug gas/15094] tic6x - opcode decoding for absdp, dpint, dpsp, dptrunc, rcpdp and rsqrdp instructions

[alexis.deruelle at gmail dot com]

http://sourceware.org/bugzilla/show_bug.cgi?id=15094

--- Comment #6 from Alexis Deruelle <alexis.deruelle at gmail dot com> 
2013-02-12 20:13:28 UTC ---
I've just applied for the requested assignment.

As I understand,  you'd like individual changelog entries for the different
parts of the patch. Is that right  ? What about the following : 

tic6x - modify opcode generation of instructions using src1 port to load
regpair lsb

After cross checking, instructions that use src2 port to load msb and src1
to load lsb value of a double precision operand into a regpair are not encoded
the same way as Ti assembler does.

Corresponding instructions are: absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp.
See SPRUFE8B.pdf p. 105, 258, 260, 262 and 418.

Ti disassembler :
- only bits 0-4 of src2 field is used to encode the regpair register numbers.
- will correctly disassemble either Ti or binutils generated opcodes

Ti assembler :
- encodes odd register number of regpair in src2 and even register number of
regpair in src1

Binutils strictly sticks to SPRUFE8B.pdf opcode definition and expects :
- src1 field to be 0
- src2 field to be even

With this patch binutils will generate the same opcode as Ti's assembler and
all opcode
variants will be correctly decoded :

* include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.

* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb)  field coding types
and use it to encode register pair numbers when required.

* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.

* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.

* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.

Cheers,

Alexis.

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